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Re: cache line size
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: cache line size
- From: "John & Ruth Pierce" <pierce@scruznet.com>
- Date: Mon, 26 Aug 1996 11:05:56 -0700
- Resent-Date: Mon, 26 Aug 1996 11:05:56 -0700
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> I am curious to know if anybody uses cache line size which is not power of 2.
This
> is specially in the context of Cache Line Wrap mode burst transfer.
>
> Thanks in advance,
> Tripathi.
Offhand, I'd think a non-power-of-two cache line would be practically
impossible. Virtually every cache scheme I've ever heard of uses various
address bits as the tag bits and index bits...
-jrp
~ p ^