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RE: PCI to PCI Bridge with 2 independant clocks
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: RE: PCI to PCI Bridge with 2 independant clocks
- From: rwalter@auspex.com (Richard Walter)
- Date: Mon, 26 Aug 1996 09:58:19 -0700 (PDT)
- Resent-Date: Mon, 26 Aug 1996 09:58:19 -0700 (PDT)
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"BoCwL.0.X-4.tVT8o"@dart>
- Resent-Sender: pci-sig-request@znyx.com
> Two quickees-
>
> Second, try buying the DEC bridge card and provide an independant clock
> for the secondary bus (rather than using the on-board PLL derived clock).
> This might require some board hacking, but should be "do-able" (don't
> you like those fancy engineering terms).
According to the datasheets for the DEC 21050, 21150, & 21152 bridges,
both the primary & secondary clocks must be the same frequency and the
skew from P_CLK to S_CLK must be between 0 and 7 ns. (ie: S_CLK must
always lag P_CLK).
> Jim Ulrich
> jimu@pathlight.com
-Richard Walter
rwalter@auspex.com
Note: I speak for myself, not for Auspex.
€ ˆ w