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RE: PCI to PCI Bridge with 2 independant clocks
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: RE: PCI to PCI Bridge with 2 independant clocks
- From: johnp@iia.com
- Date: Mon, 26 Aug 1996 09:53:47
- Priority: normal
- Resent-Date: Mon, 26 Aug 1996 09:53:47
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"CUr4q.0.hC5.BQU8o"@dart>
- Resent-Sender: pci-sig-request@znyx.com
I was under the impression that the DEC bridge chips required the clocks for
each PCI bus to be identical frequencies.
John Providenza
> From: Jim Ulrich <jimu@pathlight.com>
> Subject: RE: PCI to PCI Bridge with 2 independant clocks
> Date: Mon, 26 Aug 1996 09:29:53 -0400
> To: Mailing List Recipients <pci-sig-request@znyx.com>
> Two quickees-
>
> First, the errata about the Intel i960RP and async mode is supposedly
> for the engineering steppings only (as far as we can tell from the
> available errata sheets).
>
> Second, try buying the DEC bridge card and provide an independant clock
> for the secondary bus (rather than using the on-board PLL derived clock).
> This might require some board hacking, but should be "do-able" (don't
> you like those fancy engineering terms).
>
> Jim Ulrich
> jimu@pathlight.com
>
>
John Providenza (johnp@iia.com)
503-968-1270 (voice)
503-968-1773 (FAX)
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