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Burst reads required?



My name is William Eatherton and I am devloping a target PCI synthesis core.
I have spent many hours reading through the PCI-SIG archive on the topic
of Burst reads.  What I have found is some very definite statements
that with the Intel based PCs, a burst read instruction is never generated
from the host CPU to a PCI slave, only burst writes are generated. 

* So my question is, does anyone know of a Host-PCI bridge that generates
burst reads?  If they do, are they generated by simple memory move instructions
in compiled C, or do they require low level assembly instructions?  

	If DEC Alphas, PowerPCs, Intel PCs, and Intel clones all generate 
non-burst reads than I am thinking of not implementing the option of
burst reads at all.  I know that embedded systems are a different case and
often use burst reads and burst writes.

William Eatherton
weathert@ee.wustl.edu