RE: Burst reads required?

[Alexei Predtechenski <Alexei.Predechenski@amd.com>]

>----------
>From: 	weathert@arl.wustl.edu[SMTP:weathert@arl.wustl.edu]
>Sent: 	Wednesday, August 28, 1996 2:01 PM
>To: 	Mailing List Recipients
>Subject: 	Burst reads required?
>
>My name is William Eatherton and I am devloping a target PCI synthesis
>core.
>[...some stuff deleted...]
>	If DEC Alphas, PowerPCs, Intel PCs, and Intel clones all generate 
>non-burst reads than I am thinking of not implementing the option of
>burst reads at all.  

I do not think it is a wise decision. The CPU is not the only master on
the PCI bus. If your target has a memory-mapped buffer, it can be
directly accessed by another PCI bus-master (say, disk controller) in a
perfect burst read mode, and your design will be very "suboptimal" in
terms of bus utilization.
 - Alex
_________________________               _______
Alex Predtechenski                      \____  | Advanced 
PP Application Engineer,                /|   | |    Micro  
CPG Systems Engineering and Validation | |___| |  Devices              
(512)602-3567                          |____/ \|  
5900 E. Ben White Blvd, m/s 571        Austin, TX 78741
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