RE: Pci to Pci transfers

["jim busse" <jim_busse@email.award.com>]

At 10:23 PM 9/2/96you wrote:


At 05:02 PM 02/09/96 +0200, you wrote: 
>Hello PCI expert,
>
>I have in mind to perform direct transfers from 1 PCi master add-on board 
>to another Pi slave add-on boards (ie PCi to PCi transfers without any 
>system bus nor processor use).
>
>Is it technically feasible ?
     
     
Yes it is. Your master should start the transaction, giving the command and 
address. Some mechanism should be there to instruct the master to start the 
transaction. This mechanism may be programming by system CPU, a request 
signal from an application on the master add-on board, etc.
     
     
>What precaution should I take ?
>Is it supported by any kind of host bridge (Pentium Triton, triton2, Opti, Sys 
>Motorola MPC105 MPC106,...) ?
     
     
May be someone who has worked with these devices can give you a more 
elaborate answer but if everything is setup properly, your master wouldn't 
have any problem communicating to your target. This is what PCI is all about.
     
     
>How is performed the arbitration is a such case ? 
     
     
Since your master is on an add-on board, the arbitrator is already available 
on system motherboard. Once it receives REQ# from your master, it will 
arbitrate for that.
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     You will probably get a LOT of email on this subject.
     
     My opinion is that you are asking for extreme unreliability in X86 
     architectures.  Let me try to explain why:
     
     First, PCI bus does not support cacheing (sp?) because it lacks the 
     ability to snoop.  If you PCI-to-PCI transfer some data that is 
     currently in a piece of hardware that is waiting for the bus to allow 
     it's multi-level posting to update your target, your PCI transaction 
     will overwrite the target data, the bus will be released, and the 
     posted write activity will then take place corrupting your original 
     PCI transaction.
     
     Some cache controllers do not snoop master transfers unless the 
     internal system memory is affected.  I had trouble with a simple 
     Floppy-to-video memory driver, and could not make this robust enough 
     to work well in different machines and different operating 
     environments.
     
     In addition, for multiport RAM boards, an I/O write is typically used 
     to swap memory maps.  This does not cause a cache flush, but if you do 
     this, your driver better flush the CPU cache, because there's no 
     telling what's left over, just waiting for the next opportunity to do 
     the write-back.  It can take a long time to flush the large L2 caches 
     available in some machines.
     
     Good Luck!  Test it in LOTS of computers!!
     
     Jim Busse
     Award Software International
     
     I speak for myself, not for Award
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