RE: Burst reads required?

[Simon Cameron <simonc@Vsl.Com.Au>]

>>My name is William Eatherton and I am devloping a target PCI synthesis
>>core.
>>[...some stuff deleted...]
>>	If DEC Alphas, PowerPCs, Intel PCs, and Intel clones all generate 
>>non-burst reads than I am thinking of not implementing the option of
>>burst reads at all.  
>
>I do not think it is a wise decision. The CPU is not the only master on
>the PCI bus. If your target has a memory-mapped buffer, it can be
>directly accessed by another PCI bus-master (say, disk controller) in a
>perfect burst read mode, and your design will be very "suboptimal" in
>terms of bus utilization.
> - Alex

I understood that the DEC Alpha support chipset which interfaces the
Alpha processor to the PCI bus was capable of burst memory reads and
burst memory writes.....

Is anyone able to confirm this?

Regards,
Simon Cameron
simonc@vsl.com.au
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