Re: A BAR of 0 = disabled.

[goudreau@dg-rtp.dg.com (Bob Goudreau)]

> > >I agree that the enable bits should be OFF until a PCI board is properly set
> > >up, although, technically, any BAR set to 00000000h is disabled.
> 
> > I don't see how a BAR can be set to all 0, as there are hard-wire bits
> > in the lower 4 bit positions of a BAR.  If any of them are one, then it
> > can't be set to zero.  Perhaps you meant when the upper part of the BAR
> > is set to all zero, but I don't see where it says that in the spec. 
> 
> This came up recently in the discussion about mixing of 32-bit and 64-bit
> BARs.  On page 26 of the 2.1 spec, section 3.3.2. in the Implementation Note:
> Device Address Space, the last sentence is "Note: A Base Address register
> does not contain a valid address when it is equal to '0'".

This is true, but doesn't directly address his claim, which is that
he can't see a way for a BAR to be set to zero because of the 4
low-order bits.  The reason that claim is wrong is that those bits
certainly can be all zeroes, and definitely will be for the most
common type of Memory BAR (non-prefetchable, locate anywhere in 32-bit
space).  See section 6.2.5.1 of the spec for details.

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