RE: A BAR of 0 = disabled.

["Belvin Stephen E" <belvin_stephen_e@smtp2.space.honeywell.com>]

In a recent e-mail, Bob Goudreau (et al) wrote:

> > > > I agree that the enable bits should be OFF until a PCI
> > > > board is properly set up, although, technically,
> > > > any BAR set to 00000000h is disabled.
> > 
> > > I don't see how a BAR can be set to all 0, as there are hard-wire bits
> > > in the lower 4 bit positions of a BAR.  If any of them are one, then it
> > > can't be set to zero.  Perhaps you meant when the upper part of the BAR
> > > is set to all zero, but I don't see where it says that in the spec. 
> > 
> > This came up recently in the discussion about mixing of
> > 32-bit and 64-bit BARs.  On page 26 of the 2.1 spec,
> > section 3.3.2. in the Implementation Note:
> > Device Address Space, the last sentence is "Note: A Base Address register
> > does not contain a valid address when it is equal to '0'".

> This is true, but doesn't directly address his claim, which is that
> he can't see a way for a BAR to be set to zero because of the 4
> low-order bits.  The reason that claim is wrong is that those bits
> certainly can be all zeroes, and definitely will be for the most
> common type of Memory BAR (non-prefetchable, locate anywhere in 32-bit
> space).  See section 6.2.5.1 of the spec for details.
> 
> The PCI 2.1 specification states in an Implementation Note on page 26 that 
> 'Note: A Base Address register does not contain a valid address when it is 
> equal to "0"'.  We know from page 186, fourth paragraph that 'Read accesses 
> to reserved or unimplemented registers must be completed normally and a data 
> value of 0 returned'.

At the risk (expense) of being redundant, here is my discussion/concern on
this:

The Implementation Note is discussing the use of both an IO base address 
register and a memory base address register for accessing internal device 
registers.  It says that the configuration software will allocate (if 
possible) space to each base address register and the device driver can 
choose which base address register to actually use when it is initialized.

The device driver can choose either base address register if both were 
allocated space, but has no choice if only one base address register was 
allocated space.  There is also the possibility the none of the base address 
registers were allocated any space, so the device is completely inaccessible.

The note about a base address register value of zero being an invalid address
implies that the configuration software will write zero into any base 
address register that does not receive an address space allocation.  In 
addition, the PCI target containing a zero value base address register should 
disable address decoding for that base address register.

A literal interpretation of the note would mean that all of the bits in the 
base address register must be zero in order for the base address register to 
be disabled.  The only way this can be true for IO base address registers 
(where the LSB must be hardwired to one) and for certain variations of memory 
base registers is if a zero value written to the address field of the base 
address register forces all other bits to zero.  This actually would work 
since the configuration software writes all ones to the base address register 
(turning on the LSBs) and then counts the number of ones read back from the 
address field to determine the page size).  As long as the address field 
stays nonzero, the LSBs stay valid and everybody is happy.

A more likely interpretation of the note is that a zero value in the address 
field of the base address register should disable it and that the LSBs are 
don't care.

Is there a clear and unambiguous discussion of this issue?  Where is it?  How 
does one get a copy?

Steve Belvin

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From: goudreau@dg-rtp.dg.com (Bob Goudreau)
Message-Id: <199609051847.OAA02819@bob.rtp.dg.com>
Subject: Re: A BAR of 0 = disabled.
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