Re: A BAR of 0 = disabled.

[Charles Curley ETW <ccurley@dwarf.fc.hp.com>]

-> 
-> Hi Steve,
-> 
-> Your clarification and a second look at the implementation note (PCI2.1 3.2.2) raises 
-> a question. Is it not possible to map a PCI memory device into the bottom memory 
-> space as in this case all range bits will be zero ? How should the device driver 
-> distinguish between a genuine address space (let us say 16 MB located at bottom most
-> part) from a non-allocated memory space ?
-> 

I suppose one could take the Bill Gates Approach: *We* can't think of any
reason why you should do it, so we won't let you. :-)

More practically, many processors locate important resources at main
memory physical address 0. The 68k family has the reset vector and reset
initial stack there. The 80x8x has its interrupt vectors there. And so on.

Configuration space is wide open for the purpose, but for historical
(hysterical?) reasons, I/O space is not, and (as the Spec notes) very
crowded.

Also, most C programs and library routines assume that an address
(pointer) of 0 indicates an error rather than a valid address.


If you have an implementation where BARs are offsets from a base address
elsewhere in memory, then 0 ought to be a legal BAR. However, I would
think a more elegant way to handle it is to implement 64 bit addressing,
and relieve software of the necessity of doing the implied addition all
the time.

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Charles Curley is not an employee of Hewlett Packard.

This message does not necessarily represent the opinion(s) of HP.
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