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Re: MWI bus cycles
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: MWI bus cycles
- From: "Shivakumar S. Chonnad" <shiv@Synopsys.COM>
- Date: Fri, 6 Sep 1996 14:33:57 -0700
- Cc: pci-sig@znyx.com
- Resent-Date: Fri, 6 Sep 1996 14:33:57 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"Ytp3T2.0.vt1.ja9Co"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Hi Don,
>
> I have two (and a half) questions regarding MWI bus cycles.
>
> 1) Is it permissible for a target to assert STOP in the middle of a
> cache line during an MWI transaction?
>
> 2) If it is legal, should the following transfers by the master be made
> with MW to get to the end of the cache line, or use MWI cycles?
See pp 42 & 43 PCI2.1
Yes, a non-cacheable target can assert STOP in the middle of a cache line
during the MWI transactions. Cacheable targets must not disconnect a MWI commandexcept at cacheline boundaries whether caching is enabled or not
The master must then complete the rest of transaction using the MW command. See rule 5 pp 43, PCI 2.1
>
> 2a) If it is not legal for 2.1, what about 2.0?
I believe the above is legal for both 2.1 and 2.0
>
> Thanks for your consideration,
> Don Fry
> Sequent Computer Systems, Inc.
> (503) 578-4076 voice
> (503) 578-4850 fax
> donf@sequent.com
>
Thanks,
Shiv.
Ó ¤ “