Re: Config area (yet again)

[jww@anchor.eng.hou.compaq.com (Jeff Wolford)]

> Hi again,
> 
> I'm doing one last modification before sending my IDE driver 
> set into beta test.  It's becoming very difficult to speed 
> up this ATA device search because there's the possibility 
> for 2 separate IDE controllers being defined in the space 
> of one PCI configuration header.  This at least applies to 
> the on-board PCI chipset controllers.  Does this also apply 
> to add-on controller cards, where 2 separate controllers 
> are defined in one config header, or beyond the on-board 
> chipset controllers, is it required that the primary and 
> secondary controllers each have their own PCI config header?  
If you want to:
	1) meet SFF-8038i (aka PCI IDE Bus Mastering support)
	2) Work with the MS Win95 driver
	3) You want to support more than 2 ide devices

Then  you will be required to have both primary and secondary
controller under one configuration space and one I/O space
( BAR 4)

> I need to know if the IRQ line byte at 0x60 in the header 
> space can be relied on to be accurate, or if it only holds 
> partial info.  Currently I'm making the following assumptions:

************************************************************************
***        IRQ line at byte 0x60... What register at 0x60 ???? *********
************************************************************************

This is NOT in the PCI or SFF-8038i spec and 
not used by Compaq chip sets.

The interrupt line register is at offset 3Ch and should
be correct if both controllers are in native mode.
(Win95 only supports legacy mode, which requires two
seperate interrupts) and thus will not be correct as it
is VERY hard to support two interrupts with one location.

You start to illude to this in the last paragraph.

> 
>   o  BA 170 must use IRQ 15 (this is in the spec)
>   o  BA 1F0 must use IRQ 14 (also in the spec)
The above is only true if the device legacy mode, and then
the BARS 0-3 are not used any way.

>   o  any other non-standard base address values will not 
>      be found on the on-board chipset controllers -- is      
>      this a bad assumption?
Could be, in fact I know forsure on our laptop products where
we have a primary/secondary controller in the machine and
another primary/secondary controller in the docking station
(at different addresses of course).

>   o  any other non-standard base address is therefore
>      not an on-board controller, and the header space
>      representing this IDE controller will only represent
>      one single controller, therefore the byte at 0x60 is
>      accurate as far as the IRQ line used.
I would not make this assumption... see above for 0x60.

> The timeouts allowed by the ATA spec can go up to 31 seconds,
> therefore it's obvious why I want to eliminate any direct 
> device testing that I don't have to do.  If I can't rely on
> that byte at 0x60 to hold the correct IRQ line, then I have to
> ignore it and run the tests.  Remember that on the on-board 
> controller, both the primary and secondary channels are 
> represented in one single PCI config header and only IRQ 14
> is listed there, even though the secondary channel uses IRQ
> 15.  There is no mention of IRQ 15 in the config header.
> 

Jeff

-- 
Jeff Wolford			INTERNET: jww@compaq.com
Senior Member of Technical Staff
Advanced Architecture - Desktop Advanced Technology Development
Compaq Computer Corp
(713) 514-9465

"The views expressed here are my own, and not those of my employer."
Ô
\J