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IEEE P1996 Meeting - High Reliability PCI Bus [Sept 26] (fwd)
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: IEEE P1996 Meeting - High Reliability PCI Bus [Sept 26] (fwd)
- From: alan@znyx.com (Alan Deikman)
- Date: Fri, 6 Sep 1996 17:26:17 -0700 (PDT)
- Resent-Date: Fri, 6 Sep 1996 17:26:17 -0700 (PDT)
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"U4ypr.0.J13.m4CCo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Listmembers,
I do not normally forward postings sent to the wrong address, but
this appears to be of wide interest, and the original poster has
not responded to my suggestions to re-post.
Unfortunately, this event will be smack-dab in the middle of the
PCI Compatability workshop. If anyone knows more about this and
how well backed this effort is, I would like to hear your comment.
>>>> Forwarded message follows
From: ShawnM2298@aol.com (by way of Alan Deikman <ShawnM2298@aol.com>)
Subject: IEEE P1996 Meeting - High Reliability PCI Bus [Sept 26]
The first meeting of the P1996 High Reliability PCI Bus will be held at Santa
Clara University on Sept. 26, 1996 from 9:00 AM to 12:15 PM. This meeting
is being held in conjunction with the SCIzzl-6 meetings. For more information
on SCIzzl-6, contact chairman David Gustavson, dbg@SCIzzL.com.
Following the information I have attached an overview of the High Reliability
PCI project.
*** Registration
Email or Fax Registration Form: September 23-27, 1996, meetings
(or use the online Web form, to be available soon at www.SCIzzL.com)
Name:
Mailing Address:
City, State, Zip:
Email:
Telephone:
Fax:
SCI-related Working Group meetings September 25, 26, & 27
_____days @$200.00 (optional, one way to support SCIzzL.
No fees expected of SyncLink participants or SCIzzL corporate members)____
Less any applicable discounts (whatever you like!!) ____
IEEE International Stds. Participation Fee (usually $20/day) _______
Working-group meetings Subtotal _______
Tutorials September 23 and Workshop September 24
Early registration deadline: Sept 18 Before On or after
SCI intro Tutorial (Monday 8:30-12:15): $175 $225 _______
Technical Program (Tuesday, Sept 24): $250 $325 _______
Discount on Workshop for SCIzzL members: -$15 (credit) _______
Subtotal of registration fees: _______
Less discount on subtotal:
Company with 5 or more attending, 15%; Full-time student, 50% _______
SCIzzL corporate members receive 2 free registrations for the Workshop and
the SCI intro Tutorial (only). If you are using one of these, write the
corporate member's name here and set the total payment due to zero.
Corporate member: Total payment due: _______
Proceedings of SCIzzL-1, August 1994: $40 _______
Proceedings of SCIzzL-2, March 1995: $40 _______
Combined proc's of SCIzzL-3, 4, August/October 1995: $50 _______
Proceedings of SCIzzL-5, March 1996: $40 _______
Proceedings of SCIzzL-6, Sept. 1996: $40 _______
August 1996 special issue of IEEE Communications, "Emerging Data
Communications Standards", with articles about SCI/LAMP,
FibreChannel, 100 Base T, IsoEthernet, wireless LANs, etc. $15 _______
8-hour SCI tutorial NTSC VHS tape(Gustavson, Goodman, James) $160 _______
Publications Subtotal _______
Discount on publications for SCIzzL members: -15% (credit) _______
SCIzzL Individual Annual Membership: $59 _______
Extra charge (your estimate) for faster-than-surface shipping _______
Type of shipping you prefer ____________________________________
Total payment due: _______
Method of Payment: ___ Check (payable to "SCIzzL," drawn on a US bank)
__Visa __MasterCard (sorry, we can't take American Express)
Exact cardholder name:
Card number: Expires:
Registration may be faxed or e-mailed if paid by credit card.
SCIzzL is part of Santa Clara University, a nonprofit organization,
Federal Tax ID: 94-1156617.
SCIzzL also accepts tax-deductible donations of money or equipment.
Return this form to:
Dr. Qiang Li
Dept. of Computer Engineering
Santa Clara University
Santa Clara, CA 95053
Voice: ++1-408-554-2730, Fax: ++1-408-551-1634
Internet: SCIzzL@sunrise.scu.edu
--David B. Gustavson phone 415/961-0305 fax 415/961-3530
SCI (ANSI/IEEE Std 1596 Scalable Coherent Interface) chairman
Exec. Director, SCIzzL: Assoc. SCI Local-Area MultiProcessor Users
1946 Fallen Leaf Lane, Los Altos, CA 94024-7206 dbg@SCIzzL.com
For more info on SCI etc., see the Web: <http://www.SCIzzL.com>
***Travel arrangements:
These meetings will be held at Santa Clara University in the Engineering
Building, room 325 or at an alternate location that will be posted.
Please preregister if possible, so we will have a good estimate of
attendance for making suitable arrangements and can have badges prepared
ahead of time. Although preregistration is not mandatory, it will help a
great deal in preparing arrangements for the meeting.
Directions inside the University:
At the entrance to the University, please ask the security guards for
parking permits (free) and directions to parking lots and the meeting site.
If you arrive at a time when there is no guard present, parking permits can
be obtained from the Public Safety Office. (From the main guard house, turn
left and go one block, then left through a parking lot, then right and
watch for a short-term spot on your right and the Public Safety Office on
your left in the Cowell building).
Directions to Santa Clara University:
The University is at 500 El Camino Real, Santa Clara, which is the south
end of El Camino Real. (In some areas nearby, El Camino Real is called The
Alameda.) The University is conveniently located not far from the San Jose
airport.
The Santa Clara Mission, founded in 1777, is a famous, well-marked landmark
located on the University campus, just a few hundred meters from the
Engineering Building.
Via 101: Exit at De La Cruz Blvd., drive south on De La Cruz about 1 mile;
the road splits into two: take the right-hand side (the sign says Santa
Clara), follow the Santa Clara University sign, make a right turn on
Lafayette, and another right turn on El Camino Real. The University's
entrance is about a half mile ahead on the right-hand side of El Camino
Real.
Via Central Expressway: From Central Expressway, turn on Lafayette south,
drive about 1.4 mile, turn left on El Camino Real. The University is about
a half mile ahead on the right.
Via 280: Exit on 880 North (toward the south it is called 17). Follow
instructions for 880.
Via 880: Exit at Alameda (turn right if you come from the north, turn left
if you come from the south). Drive about 0.75 mile, the University's
entrance is on the left.
By CalTrain: Santa Clara Station is across the street from the University.
By Bus: #10 (every 30 minutes from 05:30 to 22:30) from San Jose airport
(either terminal) to Santa Clara Station, across the street from the
University, 12 minutes, $1.10.
***Hotel information:
There is a new Days Inn Hotel about a half mile from the University. A
special rate has been arranged for the meeting. All rooms have TV with
built-in VCR, refrigerator, and microwave oven. Complimentary continental
breakfast is served. The rate varies from $69 to $89 depending on the size
of the bed and whether or not you want a jacuzzi in the bathroom.
Reservations: 1-408-244-2840 or 1-800-329-7466. Identify yourself as
attending a meeting at Santa Clara University in order to receive the
discounted rate.
------- Background on P1996 -----------
Introduction to P1996 HiRelPCI
By Bob Davis, Editor
22 July 1996
Standard for an Extendible High Reliability Enhanced PCI Bus.
This bus came from a need to provide a High Reliability, High Availability
system for transportation control and telecommunications systems.
Transportation and traffic control have a need for very low system failure
rate in environmentally difficult environments. These system must operate
on the street corner from northern Alaska to the southern deserts of Arizona
with the extremes of temperature and humidity prevalent. The
telecommunications requirements are not quite as severe in the environmental
area, but are similar in the need for R.A.M. (Reliability, Availability and
Maintainability) plus the additional need of a Time Division Multiplexed bus
for circuit switched data using elements of the international Synchronous
Digital Hierarchy (SDH) at rates defined in ANSI T1.105-1991. Both areas of
usage need redundant capabilities to allow continued operation with a single
point of failure. Additional areas of interest for this project are Process
Control, Communications, and other embedded systems. These application
areas need a method of extending beyond the local bus to other similar buses
in a uniform, redundant manner. The solution to this need was to include a
provision in the bus to handle the message packets of the IEEE Std 1394-1995,
P1394.2 Serial Express and IEEE Std 1596-1992 SCI. This addition provides
for 64K addressable nodes and a uniform 64 bit address space. In more
demanding multiprocessor systems, the cache coherency methods of SCI can be
employed as needed.
This bus is designed to satisfy these needs.
1. ELEMENTS OF P1996 HiRelPCI BUS
The elements that make up this high reliability, high availability bus
include the electrical characteristics, the enhancements to include the
packet message protocols and node addressing of SCI/Serial Express, the
power, mechanical, TDM, and support signals. Each of these element are now
expanded upon.
1.1. Packet Enhanced PCI
Nominal bus signaling on the P1996 is based on the PCI Local Bus
Specification
2.1 using 3.3V signal levels. This provide access to all the silicon built
to support the PC PCI market. This protocol is flexible and provide
performance from 0 - 533 megabytes per second of read and write burst
transactions.
This bus has been extended to include a packet mode to support the packets
sent over the SCI/Serial Express busses to extend the reach to other
elements of a distributed, redundant system. Packet operations are
transparent to the normal PCI transactions and to are ignored. HiRelPCI
bus can operate in packet mode, normal PCI mode or a mix of both modes.
This mode of operation can be used to expand the normal PCI functions and
will be proposed to the PCI technical committee for inclusion in the future
PCI
Local Bus specifications.
Transparent operation is accomplished with the proposed addition of a
command mode on the PCI that is a write only mode. In this mode the
packet is a write on the bus with the high order 16 bits being used as
an address for one or more nodes to capture or indicate the failure to
capture. Write Only operations are supported in both 32 and 64 bit
wide operations that will deliver the bit serial equivalent of 4.266
gigabits per second.
Limitation on the driver technology and the physics of the backplane
restrict the number of backplane positions to 7, or 8 when stretched.
1.2. Node Addressing
Extending beyond a single PCI style bus is required for applications
that need more or vastly more processors, memory and I/O boards.
Redundant operations also require more than one processor, memory and
I/O board. Connectivity beyond a single system is greatly enhanced by
addressing card slot on a bus as a node. Each slot has a node address
consisting of 16 bits, split into 3 bits of slotid and 13 bits of address
assigned by a switch on the backplane or by a bridge to the SCI/Serial
Express node address. While this would allow 8192 buses of 8 slots each,
there may be limitations imposed by the Serial Express bus addressing
which is defined around 1024 buses of 64 nodes each. This conflict
of addressing limits has not yet been resolved yet.
These 16 pins are distributed along the connector and bypassed to ground,
or connected to ground to provide a high quality signal return path.
IEEE 1212-1991 addressing is used with these 16 bits defining a slot as
one of the 65536 in the address space. Each node has a sub address range
of 48 bits for a address space of 64 bits.
1.3. Power
Distributed power is used in this bus standard to develop the power
needed on each board in the system.
This power is distributed through dual power rails, each rail can deliver
up to 4 Amps of power at a nominal voltage of 48V to each board slot.
This nominal 48V supply has a range of 36V to 58V. This stays within
the definitions of low voltage systems and reduces the current density in
the connector pins. In telecommunication system the voltage would be
nominal 52.8 to 55V with normal batteries under charging conditions.
Addition precharge lines are located on longer pins to bring the input
circuits up to voltage before the main power pins connect. The precharge
pins are current limited to 100 mA for safety on the long pins.
The last pins to make contact on each set of power rails is the power-on
pins to start the onboard power converters.
Power rail A contain 11 pin:
4 pins P48VA
4 pins N48VA
1 pin P48VAPRE
1 pin N48VAPRE
1 pin POWERONA
Power rail B contains a similar set of pins.
The remaining two pins in the first block of pins are FGND = Frame Ground
1.4. Serial Interconnect
In addition to the primary bus, there are additional communication
systems on the backplane. These include a standard 10 Megabit Ethernet
(10Base2), and lines reserved for Fast Ethernet (100Base2), IEEE 1394-1995,
and USB.
Ethernet provide communications between the boards in the system and
through a hub located on the Central Service Module (CSM) to the outside
world for a low cost connection between bus systems.
Firewire can provide read/write capability to the boards in the system
when a redundant path is needed with a single main bus. Boards that
use this system of redundancy would all need to support the 1394 interface.
Firewire is a multimaster bus and can be used when more than one processor
is available. USB does not have this capability and may not be a good
choice in peer to peer communications for system control functions.
USB (Universal Serial Bus) is a single master connection that can be used
as a maintenance bus for testing and measurements in single master
environments.
Serial Express is added to the system through a bridge in one or
more of the bus slots. As SE devices become available, the SE bridge may
be added to the CSM function.
1.5. Support Signals
Support signals on the backplane include:
CLK10M - 10.0000 MHz Constant Clock line (accuracy to be determined)
TDO, TDI, TCK, TMS, TRST - IEEE 1149 JTAG board test lines.
nATTN - Attention Line for uninitialized boards.
CLK10M, Constant clock line, has a frequency of 10.00 MHz and is used
as a reference frequency. The bus clock in this system has a frequency
range for 0 to 66.66Mhz and may use the 0 Hz for debugging, and power
conservation functions, and can not be counted on as present for board
level functions.
Constant Clock line will provide a high accuracy reference signal for
clock and frequency generation in the system.
Each board in the system brings the JTAG board test lines out to a header
for testing.
The ATTN line is used to inform a processor of the need to initialize
a board added to the system
1.6. Mechanical
This standard uses the Hard Metric mechanical system with the
following features:
IEC 917-2-2 standard dimensions
IEEE 1301 Hard Metric Enclosures
Board top surface offset 10 mm from left reference on module
(from the front panel)
Board position allows front and back component placement
(7.23mm back, 19mm front)
30 mm front panel allows 1 inch disk drives on boards
HiRelPCI Connectors
2mm Connectors - FutureBus style - Metral style
Bellcore, UL, CSA approved
IEC 1076-4-OX (48B) compliant
EIA SP3179 compliant
Stackable connectors for I/O
Staggered Pin Height to support Live Insertion
2:1 Signal to Ground Ratio
216 pins - 4 column of 54 pins including 24 user defined I/O
pins
8 connector vendors.
HiRelPCI PACKAGING
Hard Metric formats
EMI shielding strips part of design
EMC hardened
Grounding strips on rails & cards
Tight fitting front panels
Faraday cage backplane design
Additional shielding optionally available
Fully enclosed modules for RF applications
HiRelPCI board formats
6su HiRelPCI
6su = 115mm = 4.53" x 213mm depth = 8.39"
12su HiRelPCI
12su = 265mm = 10.43" x 213mm depth = 8.39"
HiRelPCI board size comparison to VME style boards
6su HiRelPCI ~ 3u VME style
Board Size -115mm x 213mm vs. 100mm x 160mm
Board Area - 245 sq. cm vs. 160 sq. cm raw size
Usable Area - 430 sq. cm vs. 140 sq. cm component area
12su HiRelPCI ~ 6u VME style
Board Size - 265mm x 213mm vs. 233.35mm x 160mm
Board Area - 564 sq. cm vs. 374 sq. cm raw size
Useable Area - 1019 sq. cm vs. 336 sq. cm component area
1.7. Redundancy
Redundancy is provided on several levels:
Dual independent power rails
Backup serial communication for 6su style board format
Dual PCI Bus on 12su style boards
Dual TDM busses on 12su style boards
Chassis Redundancy with P1394.2 interconnec
1.8. Environmental
P1996 is intended to operate in the following environmental conditions:
Temperature -40C to +85C
Humidity 0 to 100%
Altitude -100 to +15000m
Cooling
Convection cooling for transportation applications
1.9. TDM
Dual TDM busses are included as an option for Telecommunications usage.
These busses share a common clock and frame signal. Each TDM block consists
of 6 ground pins, 1 clock pin, 1 frame pin and 2 sets of 8 data lines.
The clock pin is routed individually to each slot to provide tight timing
specification.
Simulations indicate possible clock speeds to 77.76 MHz using GTL logic
to provide an upper limit of STS12 on each of the sets of data lines.
12su systems would have dual TDM blocks for reliable redundant operation.
SDH connections provide long life
STS1 - 51.84MBits/sec - 774 Time Slots
STS3 - 155.52MBits/sec - 2322 Time Slots
STS12 - 622.08MBits/sec - 9288 Time Slots
STS24 - 1244.16MBits/sec - 18576 Time Slots
STS48 - 2.48832GBits/sec - 37152 Time Slots
1.10. CSM Functions
The Central Services Module provides the following services for the bus:
Clock drivers for each slot on the bus segment
Bus Arbitration for each slot on the bus segment
Repeater Hub for the Ethernet signals
Repeater Hub for the 1394 Firewire serial bus
Hub for the USB
Possible Bridge to Serial Express P1394.2
PCI to PCI Bridge if needed
TDM interface between outside world and backplane bus
Clocks for the TDM slots when used
Power supply from available power source to 48VDC power rails.
System monitor functions
2. FEATURES OF P1996 HiRelPCI BUS
The following set of features of the P1996 HiRelPCI Bus drive its utility:
Reliability,
Availability,
Maintainability,
Performance,
Redundancy,
Long Growth Potential
2.1. RELIABILITY
Passive Backplane
2 Signal lines per signal Return
Faraday cage signal shielding
Redundant 48V power rails
Redundant Power Supplies
Redundant busses available
Redundant Processor's available
Redundant User boards available
Low Power convection cooling
Parity on address and data
Greatly Reduced Ground Bounce
-40C to +85C Industrial/Automotive
LONGER MTBF
Choose extended temp. range parts
Redundant power supplies @ each card
Dual main supplies for A @ B rails
Low Power - less heat 3.3V bus
Faraday shielded backplane
PCI Field tested bus on PC systems
2:1 Signal to ground or ground equiv.
Proposed Bus Hold Amplifiers
Dual elements for Redundancy
Front end power supplies
User cards
Central bus resource modules
Glitch tolerant power supply with 48V (36VDC-58VDC)
2.2. AVAILABILITY
2.2.1. LOWER MTTR
Hot plugable boards
Long pins for:
Frame ground
Precharge pins
Logic ground
Short pins to enable on board power supplies
Hot plugable Power Supplies
Auto Configuration
Serial bus for Diagnostics and Control
Use logic Designed for Hot Swap
TI LVT Series
Motorola LCX Serie
2.3. MAINTAINABILITY
2.3.1. SELF CONFIGURABLE
For Simple Systems
PCI IDSEL mechanism
For Large Systems
Added node identification from SCI/Serial Express
65536 nodes addressable Per IEEE 1212 standard
2.3.2. MODULE ADDRESSING
Standard PCI with IDSEL addressing
Added 16bit geographical addressing
SA0 - SA2 select card in bus
SA3 - SA15 select bus (chassis)
8192 bus segments available
Over all master can be self selected by address 0000
this to be determined by the P1394.2 Bridge Specification
Address based back off mechanism for additional master selection in
multiple processors systems
2.4. PERFORMANCE
BANDWIDTH FOR GROWTH
Bus speeds (0 to 66.66 MHz)
33MHz x 32bits = 0 - 133 Mbytes/sec
33MHz x 64bits = 0 - 266 Mbytes/sec
66MHz x 32bits = 0 - 266 Mbytes/sec
66MHz x 64bits = 0 - 533 Mbytes/sec
VME = ~40 Mbytes/sec
ISA = ~1-5 Mbytes/sec
Additional serial busses
P1394.2 Serial Express 1.24416 - 9.95328 GBits/sec
supported by Intel, Apple, Sun
Ethernet = 10 MBits/sec
Fast Ethernet = 100 MBits/sec
IEEE 1394-1995 serial bus 100-400MBites/sec (FIREWIRE)
USB (Intel Universal Serial Bus) 12.5MBits/sec
Connected busses operate independently.
2.5. SCALABILITY
Performance in a single bus is scaleable by:
Clock Speed 0 - 66.66 MHz Determined by slowest element
Bus Width 32 or 64 bits on a transaction by transaction basis
Performance over multiple buses is scaleable by the addition
of multiple serial and/or parallel bus interconnects using
SCI/SERIAL EXPRESS techniques
2.6. REDUNDANCY
Redundancy is provided on several levels:
Redundant Elements
Redundant 48V power rails
Redundant Power Supplies
Redundant Processor's available
Redundant User boards available
Backup serial communication for 6su style board format
Dual PCI Bus on 12su style boards
Dual TDM busses on 12su style boards
Chassis Redundancy with P1394.2 interconnect.
2.7. LIFE EXPECTANCY
Lower cost silicon Available Now
Designs available for many applications
Low to high performance - Use as needed - Interchangeable
PCI to PCI bridges available
Long term growth ~ 7 years design life.
2.8. HiRelPCI Challenges
Short Life Cycle of PCI Boards
Accelerating Speed of Industry change
Slow Speed of Defense Industry change
Speed of Light (In System Environment)
8 Month to 1.5 Year Part Availability for some parts
Rapid Response to Customers Needs
Continuous design
3. IEEE PAR TITLE
Standard for an Extendible High Reliability Enhanced PCI Bus
4. IEEE PAR PURPOSE of P1996 HiRelPCI
Purpose: The transportation, telecommunications, and process control
industries need reliable high availability fault tolerant systems that
support harsh environments and extended temperature ranges, with packet
protocols that support serial interconnections to similar systems at
speeds from 10 megabits/sec to >1 gigabit/second. There is no currently
defined standard for such systems that can take advantage of the
enormous (and still growing) industrial support for the PCI system by
way of silicon, software, and tools. This standard is intended to fill
that need.
5. IEEE PAR SCOPE of P1996 HiRelPCI
Scope: This project will develop a Standard for an Extendible High
Reliability Enhanced PCI Bus for transportation, telecommunications,
and process control systems. This bus will define and use PCI-style
protocol, extending it to include packet messages as defined in the
SCI(1596-1992) and Serial Express (P1394.2) projects. This bus will
include redundancy and support hot swap of boards for fault tolerant,
high availability operation. This project will include the physical
and electrical implementation of this bus and define the interface to a
high speed serial interconnect such as the Serial Express bus. For
telecommunication applications, an optional Time Division Multiplexed
bus using international signaling rates from the Synchronous Digital
Hierarchy will be defined.
6. P1996 CHAIRMAN and EDITOR
For more information on High Reliability PCI please contact the following:
CHAIRMAN
Shawn J. Morrissey
Vice President Engineering
Intersection Development Corporation
(510)353-9415
shawnm2298@aol.com
EDITOR
Bob Davis
President
Summit Computer Systems, Inc.
(408)353-2706
bob@scsi.com
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