Only Some BARs initialized?

[rwalter@auspex.com (Richard Walter)]

Folks,

The discussion about zero'd BARs and the note in section 3.2.2 of the 2.1 spec
about requesting both I/O & Memory space for the same functionality got me
thinking this past weekend.

The note in section 3.2.2 implies that if a device requests both I/O & Memory
space for a function, then the bus configurator will allocate either I/O or
Memory or Both to that device and then the driver can pick whichever method
of talking to the device that it wants.  The note is written from the
perspective that I/O space is limited in PC systems, so you should provide
a memory space access to the same functions.

However, this assumes that configuration software could possibly allocate
only a subset of the BARs in a device.  So, a question to BIOS developers
is: Will your BIOS initialize a subset of the BARs of a device, if it can't
allocate space to all of them, or is it an all-or-nothing approach?

Assuming that there exists at least one system that would do this, would it
use the memory space & I/O space enable bits of the command register to
select which of these is active, or would it write 0's to the unused BAR?

Now, extending this idea of providing multiple accesses to the same functions
via multiple BARs, can this work with two memory BARs?  For example, suppose
that I'm making my Ultra-Super-WizBang-Cool Video chip that supports upto
16384 x 16384 x 32-bit color.  This requires a video buffer of 1 GByte.  But,
I know that many systems might not have 1 GByte of address space to allocate
to me, so I put two BARs in the device, a 1 GByte BAR for direct access, and
a 64K BAR for paged access.  Then my driver is written such that, if the
1 GByte BAR is enabled, I can talk directly to every pixel and get great
performance, and if not, then I can use the 64K window and page my way through
video memory, which would still be functional but have fairly poor performance.

However, this only works if the bus configurator will enable only some of the
BARs in a device.  But then, if the memory space & I/O space enable bits in the
command register were used to select which has been activated, then we'd have
a problem with multiple memory BARs.  Could this be the reason that the
statement about a zero BAR being disabled appears in the note and not in the
main PCI text?

Comments?

-Richard Walter
rwalter@auspex.com
Note: I speak for myself, not for Auspex.
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