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Re: Pci to Pci transfers
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: Pci to Pci transfers
- From: "Monish Shah" <monish@mcsy2.fc.hp.com>
- Date: Wed, 11 Sep 1996 09:27:08 -0600
- In-Reply-To: hsu@ocegr.fr (Herve Suquet) "Pci to Pci transfers" (Sep 11, 9:07am)
- References: <9609110707.AA21660@ocegr.fr>
- Resent-Date: Wed, 11 Sep 1996 09:27:08 -0600
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"JheBY2.0.gD.0ikDo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
On Sep 11, 9:07am, Herve Suquet wrote:
> Subject: Pci to Pci transfers
> Hello PCI expert,
>
>
>
> Some times ago I've posted an Email to have advise about PCi to Pci transfers
>
> Here is a copy of the Email :
>
> -----------------
> I have in mind to perform direct transfers from 1 PCi master add-on board
> to another Pi slave add-on boards (ie PCi to PCi transfers without any
> system bus nor processor use).
>
> Is it technically feasible ?
>
> What precaution should I take ?
> Is it supported by any kind of host bridge (Pentium Triton, triton2, Opti,
Sys
> Motorola MPC105 MPC106,...) ?
>
> How is performed the arbitration is a such case ?
> ----------------
> I received two answers. One saying that it is obvious to do and without risks
> and one saying that a lot of problem have to be faced-up making this
> almost impossible to run on various PC platforms.
>
> Between these two answers, where is the good one ?
It is in between. :-)
The first answer was correct in that if the two cards are on the same PCI
bus, that should work automatically in a properly designed system. The
other answer did not disagree with that. Rather, the author stated that
the memory that you access with peer to peer transfers would not be kept
coherent in processor caches. Of course, the author was assuming that you
were writing to memory, which may or may not be true. Also, I don't see
how you'd have a problem unless that memory was marked as cacheable by the
host. Generally, PCI memory will be marked uncacheable.
A point that wasn't made: in systems with multiple host to PCI bridges, if
the two cards wind up on two different buses, peer to peer transfers may or
may not work. It would be good to design your drivers so that they test to
see if these transfers work (at initialization) and if they don't, either
warn the user or fall back to a mode that uses normal DMA.
Another related issue is that host bridges can post memory writes. This
may introduce some ordering problems if you are not careful. The PCI spec
does have some guidelines on this.
In summary, I think it is doable, as long as you know how to deal with the
issues.
> With best regards,
> Herve
Monish Shah
Hewlett Packard
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