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Re: PCI Memory Devices
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: PCI Memory Devices
- From: Eric Ryherd <eric@vautomation.com>
- Date: Wed, 11 Sep 1996 19:47:32 -0400
- Resent-Date: Wed, 11 Sep 1996 19:47:32 -0400
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"R00iA2.0.Z62.E0rDo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
At 04:46 PM 9/10/96 -0500, you wrote:
>Hello all :),
>
>Anyone aware of sram, dram, etc. that has a pci interface?
I've acually made this request to a number of DRAM manufacturerers
and it just didn't click for some reason. Look at it this way,
with a 64M dram, you only need 1 chip for 8 Megabytes. 2 chips for the
"standard" amount installed on most PCs these days. If there are only 2 chips,
why do we need this arcane "DRAM" interface to access the chip? RAS/CAS
and all that ends up with VERY complex timing especially at the data rates
needed for a P133. Not to mention the nightmare I've been living my whole
career trying to find second sources for DRAMs that have at least some
common timing specifications or even features.
Seems to me that the PCI bus makes a VERY NICE DRAM interface standard.
And you get a high speed 32 bit interface in a 52 pin chip. PCI fits very
nicely with DRAM in that the address comes first, giving time to do the
ROW access and if the row is the same a last time, there would be
nearly no latency. Timing sure is easier than the old RAS/CAS interface...
REfresh could be completely hidden. The only really tricky bit is what
to do on power-up and configuration. After all, the system does need RAM
at boot time... Probably just have a pin that sets RAM at 0 and enables it
at power-up and requires no configuration. All the high RAM can be configed
later.
Sorry to on and on about this but this has been bugging me for years!
Eric Ryherd eric@vautomation.com
VAutomation Inc. Synthesizable HDL Cores
20 Trafalgar Sq #443 http://www.vautomation.com
Nashua NH 03063 (603)882-2282 FAX:882-1587
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