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Re: PCI Memory Devices
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: PCI Memory Devices
- From: "chefren" <chefren@pi.net>
- Date: Thu, 12 Sep 1996 03:26:19 +0100
- Comments: Authenticated sender is <hagens@pop.pi.net>
- Posted-Date: Thu, 12 Sep 1996 03:26:12 +0200 (MET DST)
- Priority: normal
- Reply-To: chefren@pi.net
- Resent-Date: Thu, 12 Sep 1996 03:26:12 +0200 (MET DST)
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"-he3_.0.TX2.oSsDo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
On 11 Sep 96 at 19:47, Eric Ryherd wrote:
...
> Seems to me that the PCI bus makes a VERY NICE DRAM interface standard.
I think it's to slow...
> And you get a high speed 32 bit interface in a 52 pin chip. PCI fits very
> nicely with DRAM in that the address comes first, giving time to do the
> ROW access and if the row is the same a last time, there would be
> nearly no latency. Timing sure is easier than the old RAS/CAS interface...
> REfresh could be completely hidden.
But it should be done! And concurrent, so arbitration or
scheduling is needed which slows down access... Maybe a
costly circuit can manage it on the pci board itself but I
think it will add heavilly to the cost. And that's
something worth d..d penalty in business...
> The only really tricky bit is what
> to do on power-up and configuration. After all, the system does need RAM
> at boot time... Probably just have a pin that sets RAM at 0 and enables it
> at power-up and requires no configuration. All the high RAM can be configed
> later.
VGA...
> Sorry to on and on about this but this has been bugging me for years!
Oh no, I like this kind of "crazy" idea's! Maybe someone
or we together could solve all problems. I don't know!
+++chefren
ï ð à