Clarifications on 3.3 volt PCI I/Os

["Raymond Gaita" <optmagic@ix.netcom.com>]

Dear PCI Experts,

One of my clients asked me to invesitigate designing a chip to be
3.3 volt PCI compliant.  There is one specification where I could use
some
clarification.  

Under AC Specifications in Section 4.2.2.2 of the spec., the high clamp
current (Ich) is specified as:

	25 + (Vin - Vcc -1)/0.015     (in mA)

If I'm interpreting this correctly, this means the I/O pins must be
capable of 
absorbing the following currents for the following Vin conditions.

	Vin	absorb current
	---	--------------
	4.3v	 25 mA
	5.3v	 92 mA
	6.3v	158 mA
	7.3v	225 mA

Does this specification apply to all pins simultaneously?  In other
words,
if there are 32 I/O pins on my PCI device, does the chip need 
to sustain a total inrush of 32 x 225mA = 7.2A through the I/O pins 
for a short period of time (which appears not to be specified in 
the specification)?  What are other designers or manufacturers doing to
handle this spec?

A similar question arises about Section 4.2.2.3, which shows an AC test
setup 
for checking device reliability.  Does the device need to withstand the
application of the waveform in Figure 4-6 (Maximum waveforms for 3.3v
signaling environment) on all pins simultaneously or just on a single
pin or some fraction of pins?

Does anyone have experience with leaving out the clamp diodes to the
3.3 volt
supply?  If the clamp diodes are left off, will the chip work in a 3.3
volt
PCI environment?  

Finally, how is PCI faring in the 3.3 volt world?  Are there many 3.3
volt PCI applications out there today? I've done a few designs for the
5 volt world already.

I am trying to get a feel for whether 3.3v PCI will have the same
success or 
whether other standards will supplant PCI by the time 3.3 volt becomes
very
widespread.  Any feedback would be greatly appreciated!


Thank you,

Raymond Gaita
OptiMagic Logic Design Studios
ö
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