[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

question on PCI spec regarding Cacheline Register

Looking at the PCI 2.1 spec, it is not 100% clear to me on the contents
of the configuration register

cacheline	cacheline 		or could it be ?
size (D words)	register		cacheline register
zero		0h			0h
four		10h			0fh
eight		20h			1fh