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question on PCI spec regarding Cacheline Register
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: question on PCI spec regarding Cacheline Register
- From: larry@mercury.RNS.COM (Larry Gerald)
- Date: Fri, 13 Sep 1996 21:50:52 -0700
- Resent-Date: Fri, 13 Sep 1996 21:50:52 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"LuuNa1.0.Qe1.xdZEo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Looking at the PCI 2.1 spec, it is not 100% clear to me on the contents
of the configuration register
cacheline cacheline or could it be ?
size (D words) register cacheline register
zero 0h 0h
four 10h 0fh
eight 20h 1fh
Comments?
8 (