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Re: question on PCI spec regarding Cacheline Register



At 09:50 PM 9/13/96 -0700, Larry Gerald wrote:
>Looking at the PCI 2.1 spec, it is not 100% clear to me on the contents
>of the configuration register
>
>
>cacheline	cacheline 		or could it be ?
>size (D words)	register		cacheline register
>zero		0h			0h
>four		10h			0fh
>eight		20h			1fh
>
>
>Comments?
>
>

Per section 6.2.4:
"This read/write register specifies the system cacheline size in 
units of 32-bit words."  

A 32-bit word is a D-word.

so: 
cacheline	cacheline size		
size (D words)	register		
zero		0h			
four		04h			
eight		08h	
sixteen         10h	

Best Regards,
Frank 9/16/96	
________________________________________________________
 Frank P. Helms 
 frank.helms@amd.com
-The opinions expressed are my own and not necessarily those of AMD.-
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