Re: Burst Accesses from Host to Target?

["John R Pierce" <pierce@scruznet.com>]

Richard Burk <RBURK@datx.com> writes...
> I'm designing a PCI target add-in card for data acquisition. I've heard   
> that there's no way to make the standard chip sets (Triton II, Triton,   
> Neptune) perform BURST reads and writes of my card. Is this true? Any   
> comments/insights would be greatly appreciated.

Burst writes are easy out of a triton etc.  Any series of writes to consecutive
DWORD aligned addresses will be merged into a burst by the triton bridge if the
host generates them faster than the target consumes them.

Burst reads aren't often (if at all) generated by the host however.  I'm not
sure ANY burst reads will occur to a non-cachable/non-prefetchable target. 
About the only way to get burst read performance is to be a bus master and do
burst writes to main memory direct.

-jrp
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