PCI DRAM Controller

[Peter Ma <ma@idacom.hp.com>]

Hi, all...

Does anyone know of a 32-bit PCI DRAM controller chip?  Feature wise, nothing
more than support for EDO devices, and support for PCI burst accesses.

I have seen host bridge chips with integrated DRAM controllers that can operate
without the host CPU (e.g. Galileo GT-64010)... but they are typically overkill
(in package size, cost, etc) for our intended application.  If possible, I would
very much like to avoid having to design around a PCI macro on a FPGA/ASIC/CPLD.

Thanks in advance... any help would be much appreciated!

Regards,
___________________________________________________________________
Peter W.W. Ma                            | email:  ma@idacom.hp.com
Design Engineer - Video Test Group       | phone:  +1 604 454-3463
Hewlett-Packard IDACOM Telecom Operation | fax:    +1 604 454-3401
#2301-4710 Kingsway Avenue, Burnaby, BC, Canada  V5H 4M2
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