[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Fast Back to Back transfers
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Fast Back to Back transfers
- From: re <roneis@lightspeed.net>
- Date: Thu, 19 Sep 1996 21:39:19 -0800
- Resent-Date: Thu, 19 Sep 1996 21:39:19 -0800
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"07AUr.0.yn4.t-YGo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Hi,
I have noticed that certain chip sets will keep FRAME# asserted when
doing reads and writes (in a tightly coded loop) to the same memory
location and target. Is this valid, and if so when does the target
sample the command lines (C/BE#) to determine what type of cycle (in
this case a memory read or a memory write)? Also should the address be
valid at this time or just on the first clock after FRAME# was asserted?
I have looked through the PCI 2.1 specification and can't find any
reference for this type of transfer. Does anyone know of a document that
shows or discusses this type of transfer?
Thanks
¨ ˜