PCI Deadlock Handling

["paul (p.n.) ramsden" <ramsden@nortel.ca>]

In the PCI Specification 2.1, section 3.3.3.2.2 "Requirements on a 
Master Because of Target Termination" it stipulates that a PCI Master 
device that implements target functionality must be able to accept 
target accesses in between RETRIES as a master. 

However, I have heard rumours that many commercial PCI mother boards 
cannot comply with this part of the specification in the situation that 
their PCI interface FIFOs become full in the case of PCI writes, or in 
the case of PCI reads, because the host cannot "back off" it's master 
cycle on the local bus. If this is true then it would mean that a 
deadlock could occur, and the system would hang due to contention in 
accesses to the LOCAL buses (as distinct from the PCI bus) if two 
master/target PCI devices initiate a master cycle to each others target 
space at the same time.

Can anyone on this reflector throw any light on whether this rumour is 
true of not?

Paul Ramsden
Dept 0X10
Nortel Technology
email ramsden@nortel.com
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