Re: PCI Deadlock Handling

["Johnson, Ralph" <ralphj@bit3.com>]

Paul,

I have observed PCI deadlocks on all 486 and Pentium motherboards I have tested 
to date.  The add-in board I used to create this condition is a PCI to VMEbus 
bridge.  Deadlocks occurred when a VMEbus initiated request to the PCI host 
collided with a PCI host request to the VMEbus.  Since VMEbus retry is not 
widely implemented, the VMEbus request must take precedence over the PCI host 
request.  This is contrary to the PCI specification because the add-in board 
target state machine is conditioned by the master state machine.  The add-in 
board will retry the PCI host access, but the PCI host will retry the add-in 
board access.  If the PCI to VMEbus bridge add-in board detects this temporary 
deadlock condition, it will BERR* the VMEbus request, backing off the VMEbus 
request to the PCI host.  Deadlocks will occur if BOTH agents on the PCI bus 
condition target responses based on the master state machine.  Deadlocks will 
occur if the host bridge has staged posted writes in its bridge and the 
requesting PCI agent again conditions its target response based on its master 
state machine.  To summarize, if PCI agents are NOT designed per PCI guidelines,
deadlocks will occur.

The PCI bus is not friendly to add-in in board bridges to buses that do not 
support retry.  Some sort of backoff mechanism would have been helpful.  Planar 
ISA and EISA to PCI bridges (and others) work because of side band signals.
It is interesting to note that the same PCI to VMEbus bridge add-in board is 
able to perform concurrent VME initiated and PCI host initiated operations in 
all Digital Alpha PCI bus platforms that I have tested to date.  I have not 
observed any deadlocks with them that would cause the BERR* mechanism to 
activate.

Ralph Johnson
ralphj@bit3.com 

______________________________ Reply Separator _________________________________
Subject: PCI Deadlock Handling 
Author:  pci-sig-request@znyx.com at Internet
Date:    09/24/96 03:30 PM


In the PCI Specification 2.1, section 3.3.3.2.2 "Requirements on a 
Master Because of Target Termination" it stipulates that a PCI Master 
device that implements target functionality must be able to accept 
target accesses in between RETRIES as a master. 

However, I have heard rumours that many commercial PCI mother boards 
cannot comply with this part of the specification in the situation that 
their PCI interface FIFOs become full in the case of PCI writes, or in 
the case of PCI reads, because the host cannot "back off" it's master 
cycle on the local bus. If this is true then it would mean that a 
deadlock could occur, and the system would hang due to contention in 
accesses to the LOCAL buses (as distinct from the PCI bus) if two 
master/target PCI devices initiate a master cycle to each others target 
space at the same time.

Can anyone on this reflector throw any light on whether this rumour is 
true of not?

Paul Ramsden
Dept 0X10
Nortel Technology
email ramsden@nortel.com
;ˆv