pci - reset#

[Francis Zerbib <research@batm.co.il>]

Hello,

I am a new user of the Intel 960RP processor. As I am designing the hardware PCI interfaces, I found
some "un-clear" description in the PCI Spec. Rev 2.1
From the spec of june 1st 95, I find on page 9 the description of the RST# signal. It is said that
 "The central resource may may derive 'AD' , 'C/BE#' , and 'PAR' (bus parking) to a logic low level during 
RST#."
On page 140, there is a diagram of the reset timing. On this diagram the PCI signals are tri-state
during RST# active.

What of these two is correct ?

Must we drive the AD[0..31] lines to logic low during RST# or leave them floating (tri-state) ?

Best regards,
 
+----------------------------------------+
| Francis Zerbib - BATM (1992)		 |
| Email: research@batm.co.il		 |
| Tel: 972-4-9894443, Fax: 972-4-9894453 |
+----------------------------------------+
U¬›