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Re: ground bounce



> What I observe is that during data phase in burst transfers, most of the input
> signals to my PCI card (e.g. frame*, irdy*, cbe*[3:0]) are glitching from low
> to high. I'm suspecting this is some sort of ground bounce effect (I also try
...
> Has anyone seen the same behavior? I would like to get your inputs. I would

Yes, we've seen this kind of thing (ground bounce) before.

>   I would
> like
> to know what needs to be done (either to the motherboard or to my PCI card) if
> this is a problem.

Ground bounce is generally an IC package phenomenon or a connector
problem.  It's often associated with the driving IC.  There may be
little you can do to the boards themselves to fix it; assuming, of
course, that you have good power and ground planes and good bypassing
at the chip pins and connector pins. 

First determine if you even have a problem.  FRAME#, IRDY#, CBEn#,
etc. are sampled only once a cycle; the rest of the time, you don't
care about their state.  Ground bounce happens when other outputs
switch, and you've got the same amount of time for the glitches to
settle, as you have for the switching AD lines to switch and settle. 
(Unless the outputs that are switching, are on a different clock
domain and can switch anywhere within a PCI cycle.)

But watch out for other asynchronous signals, like INTn# and clocks. 
Those signals require special attention around IC pinouts and
packaging to keep them clean when everything else switches.

Glitches can also happen when outputs tri-state for bus turnaround. 
That doesn't look like your problem, though.

Check the bypassing of power pins on both sides of the PCI connector. 
If, for example, the 3.3V power pins aren't bypassed on both sides,
per the specs, it will compromise the signal return path through the
connector and cause increased crosstalk.  Make sure every single power
and ground pin connects to its plane.  I've seen boards that removed
the copper from all but a few of the ground or power pins, figuring
they were sufficient.  Nope.

> The worst spike on these signals goes as high as 1.6 V (still below CMOS
> threshold). 

Below what threshold?  At 1.6V, it's closer to Vih than to Vil, in
both 5V and 3V PCI environments, and would be considered weakly if not
fully HIGH.

Regards,
Andy
j