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Re: PCI-Arbiter Extension
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: PCI-Arbiter Extension
- From: Tom Keaveny <tak@core.rose.hp.com>
- Date: Fri, 11 Oct 96 13:57:49 PDT
- Cc: pci-sig@znyx.com
- In-Reply-To: <Fri, 11 Oct 96 10:08:04 PDT_1@ccm.hf.intel.com>; from "Norman J Rasmussen" at Oct 11, 96 10:04 am
- Mailer: Elm [revision: 70.85.2.1]
- Resent-Date: Fri, 11 Oct 96 13:57:49 PDT
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"nNl_72.0.Aj5.LMhNo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Hmmm...
Would it be possible to run all of the non-bridge REQ#/GNT# pairs to
a standalone arbiter. This arbiter would then communicate to the
bridge's embedded arbiter via one of the original REG#/GNT# pairs, on
behalf of the other agents. In this way, the original bridge only
has one GNT# line of interest.
Dealing with the bridge's desire to access the bus is probably a bit
sticky (effectively an internal grant that can change on the fly),
and would likely vary according to the bridge..
==
tom keaveny
hewlett packard co.
>
> It is impossible unless the original PCI arbiter understands that a cascaded
> arbiter is to be used. Since arbitration is pipelined there are conditions in
> which two devices can believe that they own the bus.
>
> If the primary arbiter knows that a second level is supported, then the first
> arbiter must not deassert one GNT# and assert a different GNT# on the same
> clock. (WHich the spec allows while the bus is active.) The first level arbiter
> must ALWAYS cause a dead clock between the deassertion of one GNT# and the
> assertion of the next GNT#. If the arbiter never deasserts a GNT# until FRAME#
> is asserted, this can cause a hand system when a master removes its REQ# because
> it changed it mind. (THis can occur when the master enable bit is cleared.)
>
> Many have tried this with pals and such but all have failed because the first
> level arbiter did not account for a second level arbiter.
>
> Norm
t l Y