Re: [Fwd: pci - reset#]

[Andy Ingraham <ingraham@wrksys.ENET.dec.com>]

Francis Zerbib,

Below is the reply I sent out to the list almost 2 weeks ago.
Are you a member of the pci-sig maillist?  If not, you would
not have received my reply.



> From the spec of june 1st 95, I find on page 9 the description of the
> RST# signal. It is said that
>  "The central resource may may derive 'AD' , 'C/BE#' , and 'PAR' (bus
> parking) to a logic low level during 
> RST#."
> On page 140, there is a diagram of the reset timing. On this diagram
> the PCI signals are tri-state
> during RST# active.
>
> What of these two is correct ?

Page 9 is correct.  Actually, they might both be correct, although
Figure 4-12 on page 140 may be misleading.

PCI devices must tri-state PCI signals, with the exception of the
central resource which MAY pull AD, C/BE#, and PAR low.  I think the
bottom trace on Figure 4-12 is meant to show the behavior of PCI
components, which must tri-state their outputs during reset and within
t(rst-off) = 40 ns max after RST# is asserted (Table 4-6).

> Must we drive the AD[0..31] lines to logic low during RST# or leave
> them floating (tri-state) ?

Unless you are designing a central resource device, you MUST tri-state
them.  The central resource MAY park them low, but it's optional.

Regards,
Andy
x