I send this Email again, because I didnt get any reply. If I am sending this Email to a wrong address, please tell me so. Best regards, +----------------------------------------+ | Francis Zerbib - BATM (1992) | | Email: research@batm.co.il | | Tel: 972-4-9894443, Fax: 972-4-9894453 | +----------------------------------------+
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- To: sig <pci-sig@znyx.com>
- Subject: pci - reset#
- From: Francis Zerbib <research@batm.co.il>
- Date: Wed, 02 Oct 1996 15:51:38 +0300
- Organization: BATM
Hello, I am a new user of the Intel 960RP processor. As I am designing the hardware PCI interfaces, I found some "un-clear" description in the PCI Spec. Rev 2.1 >From the spec of june 1st 95, I find on page 9 the description of the RST# signal. It is said that "The central resource may may derive 'AD' , 'C/BE#' , and 'PAR' (bus parking) to a logic low level during RST#." On page 140, there is a diagram of the reset timing. On this diagram the PCI signals are tri-state during RST# active. What of these two is correct ? Must we drive the AD[0..31] lines to logic low during RST# or leave them floating (tri-state) ? Best regards, +----------------------------------------+ | Francis Zerbib - BATM (1992) | | Email: research@batm.co.il | | Tel: 972-4-9894443, Fax: 972-4-9894453 | +----------------------------------------+
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