Re: Problem w/ Matrox Millenium - Related question

[holeman@lumeria.mpd.tandem.com (Jim Holeman)]

 Brian Sassone wrote -

> I'm seeing a problem when using one of our PCI controllers in conjunction
> with a Matrox Millenium graphics card.  It appears that the Matrox card is
> retrying (for long periods of time) a mem-write (from the CPU) to its 
> address space.  Our controller gets every other bus cycle and is trying to 
> master a memory-read from system memory.  We are also getting continually
> retried until we fail (meaning that our real time requirements simply aren't
> met.)  We are seeing somewhere in excess of 256 retries.
> 
> I suspect that it is the Matrox card retrying our cycle, although I can't
> prove this.  I can't think of a reason why the host bridge would be doing 
> the retrying unless there is some strange side effect from the retries the 
> Matrox card is issuing for its own cycles.  

    The target (i.e. the host bridge) is the only device allowed to force you
    to retry.  You are the only device allowed to retry your cycles.

I believe the following is causing your problem:
    1) Host write to Matrox card has been posted to bridge.
    2) Bridge attempts to write data to Matrox card and is retried.
    3) Your card attempts to read host memory (i.e. traverse the host
       bridge).
    4) Host bridge retries your read because it has not completed its write
       on the PCI bus. (If it allowed the read, then the transactions would
       occur out of order on the host side as compared to the PCI side).
    5) Repeat 2-4 until Matrox finally accepts the host write OR your read 
       times out and you fail.

> We have tested this on two
> different Intel chipsets (HX and FX) and still see the problem.  I've also 
> heard problem reports from modem users (overruns) when using the Matrox card
> which seems to indicate the same problem.
> 
> Has anybody seen similar problems or problems with the Matrox card in
> particular? 
> Is there any explicit requirements in the PCI spec the
> prohibits a device from retrying cycles other than it's own?  

SOMEWHAT RELATED QUESTION -

 On a somewhat related note concerning the behavior of host bridges -

 PCI provides for relative fairness of allowing multiple devices to have
 access to the PCI bus.

 However, suppose that multiple high bandwidth PCI devices are attempting 
 to burst large amounts of data to host memory concurrently.  Is possible/
 likely/unlikely/? that these devices could
            a) fill all of the host bridge's PCI to memory write FIFO's
            b) cause the bridge to begin retrying subsequent PCI to memory
               write attempts until a FIFO becomes available.
            c) reach a quasi-stable condition in which one of the devices
               acquires the bus writes a burst which fills up the
               FIFO's again and releases the bus. The next device then
               acquires the bus and is retried. The first device reacquires
               the bus...just as the FIFO becomes available, fills it up 
               again, and releases the bus. The second device gets retried
               again, and so on.  Thus the first device gets its data moved
               while the second device gets starved.
 Is this paranoid, or is this feasible?  If so, are there any guarantees and/or
 ways to calculate how long such a condition could last.

 thanks,
 holeman@mpd.tandem.com







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