Delayed Transactions

[brians@Aureal.com (Brian Sassone)]

Thanks to all who responded to my question regarding retried cycles and the
Matrox Millenium.  The "problem" indeed seems to be caused by the host bridge
enforcing its transaction ordering requirements.

On delayed transactions:

PCI 2.1 states (p51) that a device is "required" to discard data when its
discard timer expires to prevent deadlocks.  Is this the same deadlock that
can occur with older PCI-to-PCI bridges described on p52?  And if so, then
is it really necessary to implement both the discard timer as well as
provide for the requirement in 3.3.3.3.4 that a target be able to accept
memory writes during completion of a delayed transaction?  And one final
point of clarification: the spec states that the risk of a discarded delayed
transaction is destroyed data due to a read to a non-prefetchable region.
Is this because it is assumed that these reads have potential side effects
on the device being read?  It seems that a discarded write would cause more
damage than a discarded read.

Brian

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Brian Sassone (brians@aureal.com)                Aureal Semiconductor
Senior Design Engineer                           4245 Technology Drive
510-252-4225                                     Fremont, California 94538
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