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Write only latency timer register
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Write only latency timer register
- From: "Wolfgang Friedrich" <friwol@iis.fhg.de>
- Date: Wed, 16 Oct 1996 16:22:51 +0200
- Organization: Fraunhofer Inst. f. Integr. Schalt.
- Priority: normal
- Resent-Date: Wed, 16 Oct 1996 16:22:51 +0200
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"maFSE.0.TE.1lGPo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Dear experts!
I'm developing a PCI add-in card working in master mode.
Transfer to system-memory is done with burst cycles longer than
2 data phases.
Is it allowed to implement the latency timer register write only?
The 2.1 specs is not very clear about this on page 193.
Any information appreciated,
Thanks for any help!
Regards,
Wolfgang.
--------------------------------
Wolfgang Friedrich FhG IIS-A
friwol@iis.fhg.de
Am Weichselgarten 5
D-91058 Erlangen-Tennenlohe
+49 (0)9131-776 506
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