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Re: Write only latency timer register
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: Write only latency timer register
- From: "Monish Shah" <monish@hpfcmss.fc.hp.com>
- Date: Wed, 16 Oct 1996 11:13:45 -0600
- In-Reply-To: "Wolfgang Friedrich" <friwol@iis.fhg.de> "Write only latency timer register" (Oct 16, 4:22pm)
- References: <DB23802D24@ep014.iis.fhg.de>
- Resent-Date: Wed, 16 Oct 1996 11:13:45 -0600
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"6mr_n3.0.Oe.yVHPo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
On Oct 16, 4:22pm, Wolfgang Friedrich wrote:
> Subject: Write only latency timer register
> Dear experts!
>
> I'm developing a PCI add-in card working in master mode.
> Transfer to system-memory is done with burst cycles longer than
> 2 data phases.
> Is it allowed to implement the latency timer register write only?
> The 2.1 specs is not very clear about this on page 193.
Page 188, section 6.2, first paragraph, last sentence:
"All registers must be capable of being read vack and the data returned
must indicate the value that the device is actually using."
That, combined with the text you read on page 193, fairly clearly implies
that your register must be read/write.
> Any information appreciated,
> Thanks for any help!
>
> Regards,
> Wolfgang.
Monish Shah
Hewlett Packard