Re: burst reads

["John R Pierce" <pierce@scruznet.com>]

Geoffrey Brown <gbrown@anise.ee.cornell.edu> wrote...
> 
> We have built an FPGA based pci board using the AMCC 5933 interface chip.
> In trials with various platforms we have found burst writes succeed, but we
> never see burst read requests on the bus (when looking with a logic
> analyzer).  Do some bridges not support burst reads ?  Are there obvious
> conditions that must be satisfied for a bridge to initiate a burst read ?  

Chances are pretty good that you won't see burst reads from the pentium host
due to various factors unless your memory is marked prefetchable and cacheable.
 Bus masters can generate burst reads.

-jrp
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