PCI Pwr Mgt, HP feedbacks

[FRANCOIS_LOISON@HP-France-om1.om.hp.com]

Item Subject: cc:Mail Text
     From: Francois Loison              Tel: (+33) (0) 4 76 14 12 55
           R&D Engineer                 Fax: (+33) (0) 4 76 14 41 27
     
           Hewlett-Packard
           Grenoble PC Division
           5 avenue Raymond Chanas
           38053 Grenoble Cedex 9
           France
     
     E-mail: francois_loison@hp.com
     
     *******************************************************************
     21st of october, 97
     
     Here are HP/CDCD (Grenoble Mainstream PC division) about
     PCI Power Management Interface spec 0.7a
     
     Abstract:
     ---------
     
     Issues:
     
     P1: PME# won't work form B3.
     P2: no power consumption maximum requirements.
     
     Limitation:
     
     L1: PMCSR mixes STS and EN bit.
     
     
     Detailed review:
     ----------------
     
     Chapter 2:
     ----------
     
     B3 state: It's said that Vcc is off. Your assumption of page 9 says
     that it apply to all bus: originating device and all devices. Spec
     says that wake-up or StatChg events are optional.
     A new PCI line PME# reports wake-up events.
     As VccAux power supply won't be provided on PCI bus, buffer of PME#
     must be VCC so this line will work from B1 and B2 but won't work with
     B3.
     
     Issue I1: PME# won't work from B3.
     
     Question: Could VccAux be provided by PCI connector? It would allow
     PME# to work on B3 also.
     
     Chapter 2.3:
     ------------
     
     Issue I2: no power consumption maximum requirements
     
     You impose PCI devices consum less than 250 mW in either D2 or D3.
     
     We strongly disagree with this requirement.
     
     We think that such a requirement isn't in the scope of this
     specification. ACPI specs don't impose maximum power consumption:
     it's Power management implementer's task. It depends on the current
     technology, the current eco labels and the wake-up functions you want
     to provide.
     
     We don't think it's a good thing to specify a very low D2 or D3 power
     consumption for ALL PCI devices:
     
     What is important is the total amount of power consummed. We should
     think of a dynamic power needs reporting and OS choses right power
     state. I think it's compliant with ACPI spirit.
     
     It's up to system manufacturers to define their global power budget,
     depending on how many PCI devices we implement, what's power budget,
     etc... Impose a minimum power to all PCI devices is expensive.
     
     Moreover, chapter 4.2.6 says that D3_Pwr reporting power consumption
     register can report up to 2.55W. If you consum 2.5W, it's not
     compliant with this spec so why implement this register?
     
     Such a value is too restrictive even if clock is stopped, you could
     recommand it. A max value of 2.55W is OK.
     
     Chapter 3:
     ----------
     
     Same issue, power consumption is global and some PCI devices can be
     allowed more power than others because they provide wake-up features.
     
     250mW isn't achievable on some devices.
     
     Chapter 4.2.4:
     --------------
     
     Limitation L1: PMCSR mixes STS and EN bit.
     
     James Kardach said we should avoid to mix En and Sts bits in same
     register, there's a multi-thread issue.
     
     
     END OF DOCUMENT
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