Re: Disabling a BAR

[goudreau@dg-rtp.dg.com (Bob Goudreau)]

> This question is really about the way the note on page 26 is worded. 
> For 
> reference: 'Note: A Base Address register does not contain a valid
> address 
> when it is equal to "0".'
> 
> A literal interpretation would conclude that the entire BAR (not just
> the 
> address field) would have to be set to zero to not contain a valid
> address.  

Or perhaps the note was just poorly worded.  Interpreting the "it"
to apply to the "address" instead of to the "register" will yield the
meaning that I think everyone believes was intended.  If that is
truly the case, the note would be better worded if it said that a
BAR whose address portion is zero does not contain a valid address.

> That doesn't really make sense since the discussion in section 6.2.5.1 
> (page 196) talks about hardwiring the LS bits.  However, it is possible 
> to design a BAR that only sets the LS bits if there is a one somewhere 
> in the address field.
> 
> My interpretation is that a BAR is 'unimplemented' if you write all ones
> 
> and read back all zeros.  Anything else is a implemented BAR.  Bit 2 
> handles the case of a 64 bit BAR with all other bits in the lower DWORD 
> hardwired to zero.  Some may quibble that reading back all zeros 
> indicates a 4Gig BAR, but I disagree since no practical system could 
> use such a device.

Count me as someone who disagrees :-).  It may be an impractical
quibble now, but who knows what the 64-bit PCI future may hold?
Several years hence, I could certainly envision a specialized video
device with a huge honkin' frame buffer.  In any case, I think your
objection fails for another reason: the spec defines a 64-bit BAR as
a single register in its own right, not as a concatenation of two
32-bit BARs.  So, a 64-bit BAR could only be said to have a
zero-valued address if *all* its address bits (including those in
the second dword) are set to zero.

> Given that an implemented BAR will read back some ones, my only 
> possible interpretation for the note on page 26 is that a zero in the 
> address field is a special case to provide a mechanism for individually 
> disabling BARs.

Back when this subject was first discussed a number of months ago,
the focus was on identifying unimplemented registers in the 24-byte
BAR range of Type 0 Configuration Space.  I believe that the note
was an attempt to cover this case.  It certainly could use some
clarification.

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