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re: PCI card current loads



Regarding the first item, I understand the comments, but if it doesn't go   
in the PCI spec, where does it go? Things like whether there are 2 or 4   
layers only affect the very high frequency component of the load current,   
which the switching power supply and bus structure cannot respond to   
anyway. I am interested in the lower frequency dynamic changes. Logic   
activity often occurs in bursts, the overall envelope of which repeats at   
some interval. The amplitude of the bursts usually has some predictable   
peak. The power supply and bus must react to the RMS amplitude and rep   
rate of the burst envelope, not the individual current changes which may   
have rise and fall times in the nanoseconds and rep rates in the hundreds   
of megahertz. Without question, there may a random or pseudo-random   
element to this logic activity, but a suitable approximation usually can   
be specified.

I view the PCI card as a generic load or black box which goes into a   
generic location called a PCI slot. I must design a power system which   
will maintain the voltage within specified limits at that slot. Two   
things make this difficult. Power systems have problems dealing with   
 dynamic changes which are a large percentage of the maximum load; a 1amp   
AC component riding on top of a 1A DC load is a lot harder to deal with   
than a 1 amp component riding on a 4A DC load. Similarly, a 1000Hz rep   
rate is harder to deal with than a 100Hz rep rate. I can see how   
specifying the rep rate is a fallible exercise given the plethora of PCI   
designs, but it certainly should be possible to put some limits on the   
permissible magnitude of the AC component.

Regarding the second item, I am not looking for the capacitance of the   
PCI backplane (which we control), but rather the capacitance of the PCI   
card itself. The amount of capacitance the power supply has to deal with   
during turn-on and other conditions is a critical item. Say that the   
"average" PCI card manufacturer builds a card with 25 microfarads on the   
5V bus and I design the power system accordingly, but some manufacturer   
decides to put 1000 microfarads on the 5V bus, perhaps because they were   
overly conservative or that was a handy place to put it to meet some   
other filtering requirement unrelated to the PCI card. Then assume I must   
provide a power system to run 4 dozen of these PCI cards. If I design to   
the "typical" card requirements but end up using this oddball, the power   
system must deal with an extra 46,800 microfarads. This may or may not be   
a problem, but certainly could be modeled ahead of time if the PCI spec   
contained a suitable  upper limit on bus capacitance.

To me, there is no distinction between PCI logic designers and PCI board   
designers. All I care about is what net PCI requirements they impose on   
my power system. I maintain that the PCI spec is the best place for the   
kind of information I am seeking. If forwarding my message above will   
help make that happen, feel free to do so.

Thanks,

Kirk

 ----------
|From:  pci-sig-request[SMTP:pci-sig-request@znyx.com]
|Sent:  Tuesday, October 22, 1996 1:16 PM
|To:  Mailing List Recipients
|Subject:  Re: PCI card current loads
|
|     Please see my reply interleaved below.
|
|______________________________ Reply Separator
|_________________________________
|Subject: PCI card current loads
|Author:  pci-sig-request@znyx.com at inet
|Date:    10/17/96 8:54 AM
|
|
|We are in the process of designing support for multiple PCI busses in a
|high end UNIX/NT system.  Our power supply guru has the following
|questions that he was unable to answer from reading the PCI spec. Anyone
|have the answers?
|
|
|I need to know two things about the PCI cards we will be using in the
|next platform. Ideally, I would like to know worst-case values, but
|realize I may have to settle for typical numbers.
|
|1) What is their dynamic load current characteristic, at the card level?
|
|For example, assume a 5V card drawing an average power of 20W. This   
could
|occur with a DC current of 4A, which would happen if all logic activity
|was perfectly filtered out by on-card capacitors. More likely, there   
would
|be some lesser DC current with an AC component riding on top. The   
question
|is: How big is this dynamic component, and what frequency is it at? I do
|not care about individual gates and signals, but rather the combined
|result of everything on the card.
|
|Is there a different answer for different cards (3.3V only, 5V only,
|Universal)?
|
|   
    ********************************************************************
|     1.) This is not covered in the PCI spec because it has nothing to   
do
|     with PCI.  This is a question of how the board is designed.  If you
|     were to design a two layer board, for example, you would have a   
much
|     worse AC component than you would with a four layer board because   
the
|     power supply and ground busses on the two layer card would have   
much
|     higher inductance than the power and ground planes on the four   
layer
|     board.
|
|     The AC component of supply current is a function of the ICs on the
|     board and their switching frequency.  There is usually some section   
of
|     the IC spec that gives dynamic current guidelines based on   
switching
|     frequency and how many outputs are driving at a given time and in   
what
|     direction.  In my experience you have to sort of interpolate your
|     dynamic current based on the guidelines in the IC spec.  It is
|     extremely difficult to get an exact number because although the   
part
|     may have a master clock input the outputs usually switch in a   
random
|     manner, which makes the output switching frequency much lower than   
the
|     master clock frequency.  You should be able to ballpark it well
|     enough, though, for most applications.
|
|     However, the dynamic supply current would not be a factor at all in   
a
|     perfect world with perfect board bypassing, except for having to
|     source the dynamic current from the supply to recharge that perfect
|     bypassing.  Since we don't live in a perfect world (at least I know   
I
|     don't!) the amount of AC ripple present on the DC supply voltage is
|     strictly a function of the AC current and how well the board   
bypassing
|     is designed.  Again, this has nothing to do with PCI or the PCI   
spec,
|     but is totally dependent on how well the board is designed.  The   
board
|     designers have to answer that question, not the spec.
|
|     I highly recommend buying a copy of Howard Johnson's "High-Speed
|     Digital Design (A Handbook of Black Magic)" from Prentice-Hall.   
 This
|     is an excellent reference on not only bypassing and board design,   
but
|     on all high speed digital issues, like crosstalk, transmission   
lines,
|     terminations and the like.  I bought my copy on a trip to San Jose   
at
|     the Computer Literacy bookstore (sorry, this isn't an ad, just a
|     reference).
|   
    ********************************************************************
|
|
|2) What is the amount of bus capacitance, at the card level?
|
|This will directly bear on how well the card filters out its dynamic
|switching currents, but I also care about how much capacitance the power
|system must charge during turn-on. Again, is there a different answer   
for
|different cards (3.3V only, 5V only, Universal)?
|
|   
    ********************************************************************
|     2.) If I understand this question correctly then you are looking   
for
|     the capacitance of the PCI backplane.  Again, this has to do with   
your
|     backplane design, including the capacitance of the pc runs, the
|     capacitance of the connectors (which should be spec'd by the
|     manufacturer) and the sum total of the capacitance of all the PCI
|     drivers on the bus (again, should be spec'd by the manufacturers of

|     the ICs driving the bus).  The runs on the bus should be   
electrically
|     short, so the capacitance can be modeled as a lumped capacitance   
(just
|     add them all together).  If the lines are not electrically short   
then
|     the capacitance must be modeled as distributed.  This distributed
|     capacitance will lower the characteristic impedence of your pc   
runs,
|     which will affect your PCI drivers.  The PCI spec *does* cover the
|     amount of min AC impedence the drivers must handle (I believe it's
|     around 30 or 32 ohms) and you calculate this number and not violate
|     it.  Again, reference the Johnson book for a good tutorial on this
|     topic.
|   
    ********************************************************************
|
| --------
|
|The PCI spec is very vague and states only that "All power planes must   
be
|decoupled to ground in such a manner as to provide for reasonable
|management of switching currents to which the plane and its supply path
|are subjected." Refer to section 4.3.4.3.
|
|Thanks in advance for any help you can provide.
|
|Kirk Soldner - Power Design
|
|   
    ********************************************************************
|     Sorry if the replies were a little too verbose. I hope that they   
helped.
|
|     Best of luck, these kinds of issues can be a real pain in the neck.
|
|     Bruce Hanahan
|     bhanahan@crosscomm.com
|
|
|
°\L