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Re: PCI DMA
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: PCI DMA
- From: John R Pierce <pierce@scruznet.com>
- Date: Thu, 24 Oct 1996 23:50:31 -0700
- Cc: pci-sig@znyx.com
- Resent-Date: Thu, 24 Oct 1996 23:50:31 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"oJADh1.0.Vl2.lD6So"@dart>
- Resent-Sender: pci-sig-request@znyx.com
At 06:50 PM 10/24/96 +100, you wrote:
>Hello,
>
>We are currently working on a project which requires intensive DMA from a PCI
>mastering device at a sustained (that is, for several seconds) bandwidth of 12
>MByte/s, with bursts of up to 20 MByte/s. We will be working with a commercial
>Pentium motherboard with loads of memory.
>Do any of you have real experience with something like this? I understand that
>the Intel Triton will accept burst writes to main memory, but will it be able
>to sustain the required data rate?
>Note that we are certainly not planning to use DOS of Windows in this project.
Shouldn't be a problem. Triton based pentium motherboards can sustain
~100MByte/sec busmastering to or from memory. SCSI controllers like the
AHA2940UW can sustain the full 40MByte/sec ultra-wide SCSI bandwidth with no
problems. The triton main memory subsystem has a bandwidth of around
200MB/s so your CPU will still have 100MB/s left over for execution etc
while doing 100MB/s PCI bursts... You will need to pay close attention to
the burst protocols of course to achieve these peak speeds... I've watched
single (non-burst) dma cycles take 3 PCI clocks consistently (33MHz/3 * 4
bytes = about 44Mbyte/sec right there but thats using 100% of the PCI
bus...) Ideally, if you do bursts of 8-16 dwords you should have no
problems... figure about 2-3 clocks of 'overhead' per burst and you'll get
there. Using 60nS EDO main memory optimizes the memory timings, and using a
512k pipeline burst cache will optimize your processor execution (especially
important with faster clock-multiplier CPUs like 166 or 200MHz).
-jrp
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