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Re: proposal to fix ordering problem in PCI 2.1

> I think this is a bad idea. The scenarios described can be avoided without
> adding such a painful extension to PCI. Only a single master should be
> allowed (that is, eligible) to access a single PCI target address at any
> one time. If multiple masters need to access the same target address, the
> system should provide some other mechanism to arbitrate between them by
> assigning "ownership" of the resource to one master at a time.

Well, taken literally, wouldn't that mean you couldn't implement
a semaphore that's shared between two pci masters?

I guess you'd have to have one intelligent agent (cpu) that would control
the starting and stopping of activity to a shared address space, 
rather than distributed control....

The current model, allows a target to resolve the 
necessary read/write behavior to make a semaphore address work properly,
as long as a single master's reads and writes are ordered to that target.
(protocol provides for a master creating such an order, for a particular

I guess you could mark certain areas as not allowing "simultaneous" access,
and not do delayed transactions for those address ranges? 

Would only have to mark these address spaces if the producer/consumer
model needed to be met, and shared access was possible.

Any semaphores would want to be low latency anyhow, so unlikely you'd
want to use delayed transactions?...hmmm...maybe not if the semaphore
exists across bus bridges