[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
PCI-Arbiter Extension
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: PCI-Arbiter Extension
- From: neumayk@kontron.de (Karl Neumayer)
- Date: Wed, 30 Oct 96 08:55:15 +0100
- Resent-Date: Wed, 30 Oct 96 08:55:15 +0100
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"va2g-.0.FV.WolTo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Hello Experts,
sorry that I arise my PCI-Arbiter question once again.
>I asked:
> ... does anyone know a reasonable way how to extend the PCI-Arbiter,
> which normally resides in the ChipSets north bridge ...
>
>Norman J. Rasmussen answered:
> It is impossible unless the original PCI arbiter understands that a
cascaded
> arbiter is to be used. Since arbitration is pipelined there are
conditions in
> which two devices can believe that they own the bus.
>
> If the primary arbiter knows that a second level is supported, then the
first
> arbiter must not deassert one GNT# and assert a different GNT# on the same
> clock...
> The first level arbiter must ALWAYS cause a dead clock between the
deassertion
> of one GNT# and the assertion of the next GNT#. If the arbiter never
deasserts
> a GNT# until FRAME# is asserted, this can cause a hand system when a master
> removes its REQ# because it changed it mind...
>
>Tom Keaveny answered:
> Would it be possible to run all of the non-bridge REQ#/GNT# pairs to
> a standalone arbiter. This arbiter would then communicate to the
> bridge's embedded arbiter via one of the original REG#/GNT# pairs, on
> behalf of the other agents. In this way, the original bridge only
> has one GNT# line of interest.
>
> Dealing with the bridge's desire to access the bus is probably a bit
> sticky (effectively an internal grant that can change on the fly),
> and would likely vary according to the bridge...
I agree with them, because that was exactly my conclusion on that problem.
But for that, I still wonder how this problem is solved by the manufacturers
of CompactPCI CPU cards (which usually employ standard ChipSets, for example
the Intel 82430FX). As far as I know, CompactPCI uses 8 Slots which should
all be capable of busmastering.
I only have a short form of the CompactPCI specification, so I do not know if
it is mandatory or optional to have all 8 Slots beeing capable of busmastering.
Any comments appreciated
Thanks,
Karl
Õ