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Re: proposal to fix ordering problem in PCI 2.1



>			  Proposed solution
>			  -----------------
>
>Four reserved pins are used to encode a Local Master ID.  This
>provides 16 distinct codes, which is more than the number of masters
>electrically feasible on a single bus.  The Arbiter knows the identity
>of the master of the current transaction and uses these four Master ID
>lines to communicate that identity to the target.
>
>  <etc.>

I came into this somewhat late, but I just got around to reading this
and it seems to me to be an unduly complex solution to this problem.
The complexity is not so much the mother-board, as the proposal seems
simple to implement there, but the target is going to be far more
involved, what with hardware lookup tables of masters, timeouts, etc.

Wouldn't it just be simpler to implement your target device in
such a way that you alias your decoded memory space N ways, where
N is the number of simultaneous masters you want to support?  Then 
each master uses a different alias for the same target entity.  
(Allocating alias images among masters will be left as an exercise 
for the student.)

For example, suppose your device implements a 1KB buffer memory,
and you want to support 16 masters.  Your BAR will now be constructed
so you are allocated 16KB instead of the "natural" 1KB.  Master
#1 accesses offsets 0-3FF, #2 access 400-7FF, etc.  The "Master
Number" is encoded into the address bits!  No semaphores, no 
modificiations to the host, no flim-flammery with the 2.1 spec.
And this will work across PCI-PCI bridges.

Did I miss something, or would this work?

Regards,

--------------------------------
  Alan Deikman, ZNYX Corporation
  alan@znyx.com
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