PCI exclusive access question

[Steven Frechette <stevenf@hw.stratus.com>]

Hi everyone,

I am designing a host bridge in an intel processor based 
system which uses the piix3 chip as the legacy expansion bus bridge. No devices 
with cacheable memory will exist on any of the PCI busses.

On page 73 of the PCI specification the following statement is made: "In 
general, LOCK# is to be used by bridges to provide backward compatibility 
for existing devices and to prevent deadlocks. A host bus bridge may need 
to support LOCK# as a target to provide backward compatibility with some 
existing add-in cards that reside behind standard expansion bus bridges."

Question: The piix3 specification makes no references to the use 
of the PCI LOCK# signal. Since this is my expansion bus bridge, is it 
reasonable to assume that my host bridge should not have to support the 
LOCK# mechanism when it is the target of a transaction. Also, does anyone 
know of any other PCI devices that would want to master a locked 
transaction upstream? Possibly graphics cards?

Steven E. Frechette                            E-Mail: stevenf@hw.stratus.com
Hardware Engineer                              Phone: 508-490-6409
Stratus Computer, Inc.
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