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Re: 66 MHz Capability bit in AGP



> From: havard@brooktree.com (havard scott)
> Subject: 66 MHz Capability bit in AGP
> Cc: dbaker@brooktree.com
> I am facing a dilemma in how to set the PCI Config Register 66 MHz
> capability bit for an AGP compliant device. We plan to be compliant
> with the 66 MHz timing requirements of the AGP bus, but not the
> more stringent 66 MHz timing requirements of the proper PCI bus. Also, 
> we intend for our chip be able to go on a PCI-33 board as well as an AGP 
> board.
> 
> This raises the question of how to set the 66 MHz capable bit. On the 
> one hand, it seems that we should set it to zero so that one could plug
> our part into the PCI bus, without incorrectly indicating that
> it is capable of 66 MHz operation. As for the case where it was on the AGP
> bus, the AGP will always run at a minimum of 66MHz, so it doesn't seem it 
> would matter whether our 66 MHz bit was set or not.
> 
> On the other hand, I'm worried about a system BIOS that will 
> have a problem with an AGP device that doesn't have it's 66 MHz
> bit set. It might decide to not enable our card. Also, for the 
> case when our device is on the true PCI bus, I'm not
> sure if it matters that we incorrectly indicate we are 66 MHz 
> capable in that environment. I am underthe impression that no system
> vendors are currently moving to implement a 66 MHz PCI bus.
> 
> I'd appreciate any feedback.
> 
> 

You could probably sample the state of the M66EN pin during RST# assertion to clear/set
the 66MHZ_CAPABLE flag of the PCI configuration space. Please refer to Section 7.5.1
66MHZ_ENABLE (M66EN) Pin definition of the PCI 2.1 spec. This is a connector pin on
the PCI bus redefined in PCI 2.1

According to the spec this connector pin value is a GND in PCI 33MHZ systems.
And in 66Mhz PCI systems it is a bussed signal that will be pulled up to high.
In an AGP board you could tie this input to ground.

Ofcourse this solution will cost you a pin. :-)

-ajoy

Rendition Inc
Mountain View
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