[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: Version 2.1 changes


The 2.1 draft version had change bars that detailed the changes 
made to the 2.0 spec. The following includes a compilation of changes 
made to the 2.1 draft to get to the 2.1 production version. It is 
not exhaustive by any means, but I hope it will be of some help.


2.0 to 2.1 highlights:
PCI Targets:
1.	Target I/O accesses with no active Byte Enables are valid 
accesses and terminate normally.
2.	Target accesses must be completed within 16 clocks from the 
assertion of FRAME#. All accesses that would normally require more 
than 16 clocks to complete must be completed with retry within 16 
clocks and completed as a delayed transaction on a retried cycle when 
the device is ready to complete the transaction. Tolerance of older 
PCI masters is supported by discarding the delayed transaction if it 
isn't returned within 2^15 PCI clocks of the delayed transaction request.
3.	It is recommended that targets that detect illegal PCI events, 
such as FRAME# and IRDY# being de-asserted on the same clock, should 
"gracefully" move to the idle state. Grace should at least consist of 
returning sustained three state signals that are being driven by the 
target to their de-asserted state and three stating them.
4.	To avoid deadlocks while completing a delayed transaction 
request, the target must complete all memory writes while waiting for 
completion of the delayed request.

PCI Masters:
1.	Masters must repeat a read or write transaction that is 
terminated with retry.
2.	Masters must assert IRDY# within 8 clocks during all data 
phases. Preferably, IRDY# should be asserted with no delay on all 
data phases.

2.1 draft to 2.1 production differences
* Command Usage:

  The draft spec recommends that the Memory Read command should be
  used for reading upto a cacheline, the Memory Read Line to be used
  for reading one cacheline.

  The prodn spec recommends that the memory read command should be
  used for reading a single DWORD, and the Memory Read Line is to be
  used for reading more than a DWORD to an entire cacheline.

  Note that they are recommendations only.

* Transaction 3.2.5

  This section is totally new and has been added.

  There are very strict rules in this section for ordering, especially
  for bridges.  It assumes the Producer-Consumer Model given in the
  appendix.  Some requirements are listed which will need some serious
  looking-into for ALL designs.

* Requirements on a master for a target termination

  This topic has existed earlier, but it has been collected and put as
  one single section.  What it essentially says (like before too) is that
  when a master receives a STOP#, it must deassert its request for two
  clocks.  But in the production version, he makes one exception.  He
  says that the master is not required to deassert its ERQ# when the
  target requests the transaction to end by asserting STOP# in the
  last data phase.

  This can be ignored in existing designs.  All it does is not deassert
  REQ# unnecessarily.

* Delayed transactions

  This section has been changed.  Some timers are added.  Needs serious
  looking into (esp. sections and by devices implementing
  delayed completion.

Additional notes:

Sections 3.11 (Special Design Considerations) and Appendix E (System
Transaction Ordering) need to be seen and checked against all designs
which hope to be 2.1 compliant.

Frank Story                    frank.story@tempe.vlsi.com
VLSI Technology                602-752-6098
Computing Products Group