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Re: 66 MHz Capability bit in AGP
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: 66 MHz Capability bit in AGP
- From: png@woof.net (Peter N. Glaskowsky)
- Date: Tue, 5 Nov 1996 19:47:06 -0800
- Resent-Date: Tue, 5 Nov 1996 19:47:06 -0800
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"GPRrZ3.0.uF2.og1Wo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
> If you PCI (not AGP) card grounds the M66EN pin, it had better also make
> the 66 MHz capable bit false. The host is free to look at either one to
> decide which frequency it should run at.
Um, I don't think so. Doesn't a grounded M66EN pin _force_ the bus to 33
MHz? The central resource has to do this, I thought. My spec's at work, and
you know, there's no electronic version on the Web anywhere. Someday I'm
just gonna set OmniPage Pro to work on it, if only for myself. (Yeah, I
know, the PCI SIG makes money from selling paper copies. If you're
listening, guys-- please join us here in the 20th Century before it becomes
the 21st, okay?)
> If you really want to build silicon to work either as AGP or as PCI, you
> should either just design to 66 MHz PCI timing or burn a pin on the chip to
> tell you whether you're on a PCI board or an AGP board and set the 66 MHz
> capable flag accordingly.
I think it's reasonable to be 33-MHz PCI or 66-MHz AGP; you may never see a
66-MHz PCI slot anywhere. It's also reasonable not to want to lose a pin on
the chip. I've seen chips squeezed into a 208-PQFP that really should have
been put in a 240-PQFP, just for cost reasons. If someone's going to that
trouble, adding a pin for a function that's only used for about 5 ns after
RESET* is deasserted is rather unattractive.
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