Please explain rule 1 of Target Termination Signaling rules

[denniss@lmc.com]

Hello PCI experts,

Could someone please explain a few things about rule 1 of
the target termination signaling rules (3.3.3.2.1) ??


On page 42:

1. A data phase completes on any rising edge on which IRDY# is
   asserted and either STOP# or TRDY# is asserted.
   
Furthur down the page...   
   
Rule 1 means that a data phase can complete with or without TRDY#
being asserted. When a target is unable to complete a data transfer,
it can assert STOP# without asserting TRDY#.

I undersatand the above. I do not understand the next line:

When both FRAME# and IRDY# are asserted, the master has committed
to complete two data phases.


If STOP# is asserted on first data phase of a two data phase transaction
(without TRDY# being asserted - no data transfered), what 
distiguishes that two complete data phases has occured on the bus ???
In other words, how do I know by looking at the pci signals that the
second data phase occured?


Thank you in advance! 
ýL;