RE: Please explain rule 1 of Target Term

[Braun_Josef#Tel3805 <bj3805@denbgm31m.scnn1.msmgate.m30x.nbg.scn.de>]

>When both FRAME# and IRDY# are asserted, the master has committed
>to complete two data phases...

does not mean, that this data phases will occur; it depends on the 
respective
target. The master only shows his intention, to transfer to DW. If he wanted 
to
complete only one data phase, FRAME# would be deasserted while IRDY#
remains asserted!

jbm

 ----------
Von: pci-sig-request
An: Mailing List Recipients
Betreff: Please explain rule 1 of Target Termination Signaling rules
Datum: Donnerstag, 7. November 1996 21:15

Hello PCI experts,

Could someone please explain a few things about rule 1 of
the target termination signaling rules (3.3.3.2.1) ??


On page 42:

1. A data phase completes on any rising edge on which IRDY# is
   asserted and either STOP# or TRDY# is asserted.

Furthur down the page...

Rule 1 means that a data phase can complete with or without TRDY#
being asserted. When a target is unable to complete a data transfer,
it can assert STOP# without asserting TRDY#.

I undersatand the above. I do not understand the next line:

When both FRAME# and IRDY# are asserted, the master has committed
to complete two data phases.


If STOP# is asserted on first data phase of a two data phase transaction
(without TRDY# being asserted - no data transfered), what
distiguishes that two complete data phases has occured on the bus ???
In other words, how do I know by looking at the pci signals that the
second data phase occured?


Thank you in advance!

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