Re: endian-ness

[Adam Barnes <amb@transtech.co.uk>]

Brian Sassone wrote:

>> Does a PCI bus master designed for an Intel based system need to perform
>> byte swapping when running on a PowerPC?

This is a favourite topic of conversation at my company. Just getting the
terminology right can be confusing. For example, some people make
a distinction between endian-ness (bit ordering) and addressian-ness
(byte ordering).

There are two cases that we have tried to address.
One arises when multiples of a short data type (say a byte)
are transferred within a larger data type (say a Dword).
Here the size information gets lost and the different byte
ordering conventions in big-endian and little-endian environments
show up.

To illustrate this:
If a bus master is sending 32-bit words into the the memory
of a big-endian host CPU, that CPUs PCI bridge should apply
byte lane steering appropriate to 32-bit cycles, and ensure
that the PCI MSB and LSB go to the MSB and LSB of a 32-bit
memory location correctly.
If, however, the bus master is sending an array of bytes
into the memory using 32-bit cycles (as will almost always
be the case), the bridge sees no difference and it will
screw up the ordering of bytes. The CPU will end up seeing
bytes in its memory like so: 3,2,1,0,7,6,5,4...

The other case is where you have a rigid policy in the CPU-PCI
bridge - usually this will be 'byte invariant addressing'.
An example of this is the Tundra Universe PCI-VME bridge.
This is fine for byte data but guarantees 32-bit data will
be swapped.

The bottom line is this: if you can offer software configurable
byte swapping, you (or at least your software team) will be
glad you did. You should at least offer a full byte swap mode
and if you're planning to trade 16-bit data types, one for that
would be nice too. The application of any swapping should probably
be limited to (say) an alias of your device's slave image. This makes
sure things like configuration cycles don't get messed up. As a master
you could just add some bits to a control register.

Note that all of this applies to 32-bit PCI. I don't want to think
about PCI-64!

Adam Barnes
Transtech Parallel Systems
amb@transtech.co.uk
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