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Question: related to System bus bandwidth
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Question: related to System bus bandwidth
- From: subbarao@rd.smos.com (Arumilli Subbarao 12/08/95)
- Date: Fri, 15 Nov 1996 12:52:08 -0800
- Resent-Date: Fri, 15 Nov 1996 12:52:08 -0800
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"YPFzy3.0.Q55.ucDZo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Hi
I have a question regarding the calculation(observation) of the bus bandwidth.
For PCI we can plug Logic analyzer and observe the transactions. (basically
using one pci slot). But how do we do this for processor-memory system bus. We
cant attach logic analyzer to processor pins or chipset pins (because very
narrowly soldered). Is there any way.
We want to profile the system bus utilization. Any pointers are welcome.
Thanks
SUbbarao.
8 %